CS53L21-DNZ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS53L21-DNZ

Low Power, Stereo Analog to Digital Converter

Cirrus Logic 

CS53L21

15.REVISION HISTORY

Revision

Changes

A1

Initial Release

Adjusted the minimum voltage specification in “Specified Operating Conditions” section on page 11.

Adjusted maximum “Analog In to PGA to ADC” THD+N performance specification in “Analog Characteristics

(Commercial - CNZ)” on page 12.

Corrected Interchannel Gain Mismatch specification in “Analog Characteristics (Commercial - CNZ)” on page 12

and “Analog Characteristics (Automotive - DNZ)” on page 13.

Adjusted ADC full scale input voltage specification in “Analog Characteristics (Commercial - CNZ)” on page 12

and “Analog Characteristics (Automotive - DNZ)” on page 13.

Removed td timing specification from table in section “Switching Specifications - Serial Port” on page 14.

Corrected Group Delay characteristic in table in section “ADC Digital Filter Characteristics” on page 14.

Adjusted timing specifications td(MSB) from 40 ns to 52 ns and ts(SDO-SK) from 30 ns to 20 ns in table in section

“Switching Specifications - Serial Port” on page 14.

PP1 Adjusted I²C timing specifications tack from 1000 ns to 3450 ns in table in section “” on page 15.

Modified the Typ. Conn. HW and SW figures by adding a pull-up to the VA_HP pin and changed AFILTA, B cap

values from 1000 pF to 150 pF.

Modified the Pin Descriptions table description for pin 5 to add a pull-up.

Adjusted High-Level Input Voltage specifications VIH from 0.65VL to 0.68VL and VIL from 0.35VL to 0.32VL in

table in section “Digital Interface Specifications & Characteristics” on page 18.

Adjusted the +20 dB Digital Boost block before the ALC feedback path in Figure 7 on page 22.

Modified ALC Recommended Settings in section “Automatic Level Control (ALC)” on page 26.

Modified step 2 of the “Recommended Power-Down Sequence” on page 33.

Corrected default values for ALC and Limiter Release Rates shown in “Register Quick Reference” on page 37.

Corrected default value for the SPE_SZC bits in “SPE Control (Address 09h)” on page 48.

Corrected ADC Filter Response shown in Figures 23, 24, 25, and 26 on page 60.

Corrected ADC_SNGVOL description in “MIC Control (Address 05h)” on page 44.

64

DS700PP1

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