CS53L21-DNZ View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS53L21-DNZ

Low Power, Stereo Analog to Digital Converter

Cirrus Logic 

CS53L21

Function:

Sets the rate at which the ALC releases the PGA & digital attenuation from levels below the minimum setting

in the ALC threshold register, and returns the input level to the PGA_VOL[4:0] & ADCx_ATT[7:0] setting.

The ALC release rate is user selectable, but is also a function of the sampling frequency, Fs, and the SOFTx

& ZCROSS bit settings unless the disable bit for each function is enabled.

6.15 ALC Threshold (Address 1Eh)

7

MAX2

6

MAX1

5

MAX0

4

MIN2

Maximum Threshold (MAX[2:0])

Default: 000

MAX[2:0]

000

001

010

011

100

101

110

111

Threshold

Setting

(dB)

0

-3

-6

-9

-12

-18

-24

-30

3

MIN1

2

MIN0

1

Reserved

0

Reserved

Function:

Sets the maximum level, relative to full scale, at which to limit and attenuate the input signal at the attack

rate.

Minimum Threshold (MIN[2:0])

Default: 000

MIN[2:0]

000

001

010

011

100

101

110

111

Threshold

Setting

(dB)

0

-3

-6

-9

-12

-18

-24

-30

Function:

Sets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at a rate set

in the release rate register until levels again reach this minimum threshold. The ALC uses this minimum as

a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the

minimum setting. This provides a more natural sound as the ALC attacks and releases.

DS700PP1

53

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