CS53L21-DNZR View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS53L21-DNZR

Low Power, Stereo Analog to Digital Converter

Cirrus Logic 

CS53L21

6. REGISTER DESCRIPTION

All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are

read only. See the following bit definition tables for bit assignment information. The default state of each bit after a

power-up sequence or reset is listed in each bit description.

All “Reserved” registers must maintain their default state.

6.1 Chip I.D. and Revision Register (Address 01h) (Read Only)

7

Chip_ID4

6

Chip_ID3

5

Chip_ID2

4

Chip_ID1

3

Chip_ID0

2

Rev_ID2

1

Rev_ID1

0

Rev_ID0

Chip I.D. (Chip_ID[4:0])

Default: 11011

Function:

I.D. code for the CS53L21. Permanently set to 11011.

Chip Revision (Rev_ID[2:0])

Default: 001

Function:

CS53L21 revision level. Revision B is coded as 001. Revision A is coded as 000.

6.2 Power Control 1 (Address 02h)

7

Reserved

6

Reserved

5

Reserved

4

3

2

1

PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA

0

PDN

Notes:

1. To activate the power-down sequence for individual channels (A or B,) both channels must first be pow-

ered down either by enabling the PDN bit or by enabling the power-down bits for both channels. En-

abling the power-down bit on an individual channel basis after the A/D has fully powered up will mute

the selected channel without achieving any power savings.

2. Reserved bits 5 and 6 should always be set “high” by the user to minimize power consumption during

normal operation.

Recommended channel power-down sequence: 1.) Enable the PDN bit, 2.) enable power-down for the se-

lect channels, 3.) disable the PDN bit.

40

DS700PP1

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