CS5376A-IQZ(2005) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5376A-IQZ Datasheet PDF : 108 Pages
| |||
CS5376A
9.3.2 SPI 1 registers
The SPI 1 registers are shown in Figure 19 and are
24-bit registers mapped into an 8-bit register space
as high, mid, and low bytes. See “SPI 1 Registers”
on page 82 for the bit definitions of the SPI 1 reg-
isters.
MOSI: 03 01 00
MISO: xx xx 12
5-byte read transaction of SPI1DAT1
MOSI: 03 06 00 00 00
MISO: xx xx 12 34 56
9.3.3 SPI 1 transactions
A serial transaction to the SPI 1 registers starts with
an SPI opcode, followed by an address, and then
some number of data bytes written or read starting
at that address.
Typical serial write transactions require sending
groups of 5, 8, or 11 total bytes to the SPI1CMD or
SPI1DAT1 registers.
Example 5-byte write transaction to SPI1CMD
02 03 12 34 56
Example 5-byte write transaction to SPI1DAT1
02 06 12 34 56
Example 8-byte write transaction to SPI1CMD
02 03 12 34 56 AB CD EF
Example 8-byte write transaction to SPI1DAT1
02 06 12 34 56 AB CD EF
Example 11-byte write transaction to SPI1CMD
02 03 12 34 56 AB CD EF 65 43 21
Typical serial read transactions require groups of 3
or 5 bytes, split between writing into MOSI and
reading from MISO.
3-byte read transaction of mid-byte of SPI1CTRL
9.3.4 Multiple serial transactions
Some configuration commands require multiple se-
rial transactions to complete. There must be a small
delay between transactions for the CS5376A to
process the incoming data. Three methods can be
used to ensure the CS5376A is ready to receive the
next configuration command.
1) Delay a fixed 1 ms period to guarantee enough
time for the command to be completed.
2) Monitor the SINT pin for a 1 us active low pulse.
This pulse output occurs once the CS5376A com-
pletes processing the current command.
3) Verify the status of the E2DREQ bit by reading
the SPI1CTRL register. When low, the CS5376A is
ready for the next command.
9.3.5 Polling E2DREQ
One transaction type that can always be performed
no matter the delay from the previous configuration
command is reading E2DREQ in the mid-byte of
the SPI1CTRL register. A 3-byte read transaction.
MOSI: 03 01 00
MISO: xx xx 01 <- E2DREQ bit high
MISO: xx xx 00 <- E2DREQ bit low
Name
SPI1CTRL
SPI1CMD
SPI1DAT1
SPI1DAT2
Addr.
00 - 02
03 - 05
06 - 08
09 - 0B
Type
R/W
R/W
R/W
R/W
# Bits
8, 8, 8
8, 8, 8
8, 8, 8
8, 8, 8
SPI 1 Control
SPI 1 Command
SPI 1 Data 1
SPI 1 Data 2
Description
Figure 19. SPI 1 Registers
34
DS612F3
Share Link: 