CS5376A(2004) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376A
(Rev.:2004)

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376A

command and the low byte designated as an ad-

dress. The high byte holds an 8-bit SPI ‘write’ or

‘read’ opcode, as shown in Figure 40, and the low

byte holds an 8-bit serial address.

During a transaction, bits in SPI2CMD are output

MSB first, with data in SPI2DAT written or read

following.

20.3.3 SPI 2 Data Register

The SPI2DAT register (0x12) is a 24-bit digital fil-

ter register containing three SPI data bytes. Data in

SPI2DAT is always LSB aligned, with 1-byte data

written or received using the low byte, 2-byte data

written or received using the middle and low bytes,

and 3-byte data written or received using all three

bytes.

Data in SPI2DAT is written or read after writing

the command and address bytes from the

SPI2CMD register.

20.4 SPI 2 Transactions

The SPI 2 port operates as an SPI master to perform

write and read transactions with serial slave periph-

erals. The exact format of the SPI transactions de-

pends on the SPI mode, selected using the SCKPO

and SCKPH bits in the SPI2CTRL register.

Write Transactions

Write transactions start by writing an SPI ‘write’

(0x02) opcode and an 8-bit destination address into

the SPI2CMD register and the output data value to

the SPI2DAT register. Writing the D2SREQ bit in

the SPI2CTRL register initiates the SPI 2 transac-

tion based on the SPI2CTRL configuration.

A write transaction outputs 1 or 2 bytes from the

SPI2CMD register followed by 1, 2, or 3 bytes

from the SPI2DAT register. Write transactions are

therefore a minimum of 1 byte (DNUM = 0) and a

maximum of 5 bytes (DNUM = 4). The SPI 2 port

uses the DNUM bits in the SPI2CTRL register to

determine the total number of bytes to send during

a write transaction.

Write transactions are not required to use standard

SPI commands. If serial peripherals use non-stan-

dard write commands they can be written into

SPI2CMD and SPI2DAT as required.

Read Transactions

Read transactions start by writing an SPI ‘read’

(0x03) opcode and an 8-bit source address to the

SPI2CMD register. Writing the D2SREQ bit in the

SPI2CTRL register initiates the SPI 2 transaction

based on the SPI2CTRL configuration, with the

data value automatically received into the

SPI2DAT register.

A read transaction outputs 2 bytes from the

SPI2CMD register and can receive 1, 2, or 3 bytes

into the SPI2DAT register. Read transactions are a

minimum of 3 bytes (DNUM = 2) and a maximum

of 5 bytes (DNUM = 4). The SPI 2 port uses the

DNUM bits in the SPI2CTRL register to determine

the total number of bytes to send and receive during

a read transaction.

Read transactions are not required to use standard

SPI commands. If serial peripherals use non-stan-

dard read commands they can be written to the

SPI2CMD register, as long as they conform to the

format of 2 bytes out with 1, 2, or 3 bytes in.

SPI Modes

The SPI mode for the SPI 2 port is selected in the

SPI2CTRL register using the SCKPO and SCKPH

bits. The most commonly used SPI modes are

mode 0 and mode 3, both of which define the serial

clock with data valid on rising edges and transition-

ing on falling edges.

In SPI mode 0, the SCK2 serial clock is defined ini-

tially in a low state. Output data on the SO pin is

valid immediately after the chip select pin goes

low, and the first rising edge of SCK2 latches valid

data.

73

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