CS5504-BS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5504-BS

Low Power, 20-Bit A/D Converter

Cirrus Logic 

PIN DESCRIPTIONS*

CS5504

CS5504

MULTIPLEXER SELECTION INPUT

CHIP SELECT

CONVERT

CALIBRATE

CRYSTAL IN

CRYSTAL OUT

BIPOLAR/UNIPOLAR

DIFFERENTIAL ANALOG INPUT

DIFFERENTIAL ANALOG INPUT

DIFFERENTIAL ANALOG INPUT

A0

CS

CONV

CAL

XIN

XOUT

BP/UP

AIN1+

AIN2+

AIN1-

1

20 DRDY DATA READY

2

19 SDATA SERIAL DATA OUTPUT

3

18 SCLK SERIAL CLOCK INPUT

4

17

VD+

POSITIVE DIGITAL POWER

5

16 DGND DIGITAL GROUND

6

15

VA-

NEGATIVE ANALOG POWER

7

14

VA+

POSITIVE ANALOG POWER

8

13 VREF- VOLTAGE REFERENCE INPUT

9

12 VREF+ VOLTAGE REFERENCE INPUT

10

11

AIN2-

DIFFERENTIAL ANALOG INPUT

*Pinout applies to both PDIP and SOIC

Clock Generator

XIN; XOUT - Crystal In; Crystal Out, Pins 5, 6.

A gate inside the chip is connected to these pins and can be used with a crystal to provide the

master clock for the device. Alternatively, an external (CMOS compatible) clock can be

supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the

device into a lower powered state (approximately 70% power reduction).

Serial Output I/O

CS - Chip Select, Pin 2.

This input allows an external device to access the serial port.

DRDY - Data Ready, Pin 20.

Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new

output word has been placed into the serial port. DRDY will return high after all data bits are

shifted out of the serial port or two master clock cycles before new data becomes available if

the CS pin is inactive (high).

SDATA - Serial Data Output, Pin 19.

SDATA is the output pin of the serial output port. Data from this pin will be output at a rate

determined by SCLK. Data is output MSB first and advances to the next data bit on the falling

edges of SCLK. SDATA will be in a high impedance state when not transmitting data.

SCLK - Serial Clock Input, Pin 18.

A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin

must not be allowed to float.

20

DS126F21

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