CS5467-ISZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5467-ISZ Datasheet PDF : 46 Pages
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CS5467
8.2.13 Control (Ctrl) – Address: 28
23
22
21
20
19
18
17
16
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
15
14
13
12
11
10
-
-
-
I2gain
-
-
9
8
-
STOP
7
6
5
4
3
2
1
0
-
-
I1gain
INTOD
-
NOCPU
NOOSC
-
Default = 0
PC[7:0]
I1gain (I2gain)
STOP
INTOD
NOCPU
NOOSC
Phase compensation for channel 2. Sets a delay in voltage relative to current. Phase is
signed and in the range of -1.0 ≤ value < 1.0 sample (OWR) intervals.
Sets the gain of the current1 (current2) input.
0 = Gain is set for ±250mV range.
1 = Gain is set for ±50mV range.
Terminates E2PROM command sequence (if used).
0 = No Action
1 = Stop E2PROM Commands.
Converts INT output pin to an open drain output.
0 = Normal Output
1 = Open-drain Output
Saves power by disabling the CPUCLK output pin.
0 = CPUCLK Enabled
1 = CPUCLK Disabled
Disables the crystal oscillator, making XIN a logic-level input.
0 = Crystal Oscillator Enabled
1 = Crystal Oscillator Disabled
DS714F1
33
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