CS5464 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5464

Three-channel, Single-phase Power/Energy IC

Cirrus Logic 

CS5464

5. FUNCTIONAL DESCRIPTION

5.1 Analog Inputs

The CS5464 is equipped with three fully differential in-

put channels. The inputs VIN±, IIN±, and IIN2± are des-

ignated as the voltage, current, and current 2 channel

inputs, respectively. The full-scale differential input volt-

age for the current and voltage channel is ±250 mVP.

5.1.1 Voltage Channel Input

The output of the line voltage resistive divider or trans-

former is connected to the VIN+ and VIN- input pins of

the CS5464. The voltage channel is equipped with a

10x fixed-gain amplifier. The full-scale signal level that

can be applied to the voltage channel is ±250 mV. If the

input signal is a sine wave, the maximum RMS voltage

at a gain 10x is:

2---5---0----m-----V---P--

2

≅

176.78 m

VR

MS

which is approximately 70.7% of maximum peak volt-

age. The voltage channel is also equipped with a Volt-

age Gain Register, allowing for an additional

programmable gain of up to 4x.

5.1.2 Current Channel Inputs

The output of the current-sense resistor or transformer

is connected to the IIN+ (IIN2+) and IIN- (IIN2-) input

pins of the CS5464. To accommodate different cur-

rent-sensing elements, the current channel incorpo-

rates a programmable gain amplifier (PGA) with two

programmable input gains. Configuration Register bit

Igain (I2gain) defines the two gain selections and corre-

sponding maximum input signal level.

Igain, I2gain

0

1

Maximum Input

±250 mV

±50 mV

Gain

10x

50x

Table 1. Current Channel PGA Setting

For example, if Igain=0 (I2gain=0), current channel 1(2)

PGA gain is set to 10x. If the input signals are pure si-

nusoids with zero phase shift, the maximum peak differ-

ential signal on the current or voltage channel is

±250 mVP. The input signal levels are approximately

70.7% of maximum peak voltage and produce a

full-scale energy pulse registration equal to 50% of ab-

solute maximum energy registration. This will be dis-

cussed further in See Section 5.5 Energy Pulse Output

on page 18.

The Current Gain Register also facilitates an additional

programmable gain of up to 4x. If an additional gain is

applied to the voltage and/or current channel, the maxi-

mum input range should be adjusted accordingly.

5.2 IIR Filters

The current and voltage channels are equipped with a

3rd-order IIR filter, that is used to compensate for the

magnitude roll off of the low-pass decimation filter.

5.3 High-pass Filters

By removing the offset from either channel, no error

component will be generated at DC when computing the

active power. By removing the offset from both chan-

nels, no error component will be generated at DC when

computing VRMS, IRMS, and apparent power. Operation-

al Mode Register bits VHPF, VHPF2, IHPF and IHPF2

activate the HPF in the voltage and current channel, re-

spectively. When a high-pass filter is active in only one

channel, an all-pass filter (APF) is applied to the com-

panion channel. The APF has an amplitude response

that is flat within the channel bandwidth and is used for

matching phase in systems where only one HPF is en-

gaged.

VHPF(2) IHPF(2)

Filter Configuration

0

0

All Filters Off on Channel 1(2)

0

1

HPF on Current Channel 1(2)

1

0

HPF on Voltage Channel 1(2)

1

1 HPF on Current & Voltage Channels 1(2)

Table 2. High-pass Filter Configuration

5.4 Performing Measurements

The CS5464 performs measurements of instantaneous

voltage (Vn) and current (In), and calculates instanta-

neous power (Pn) at an output word rate (OWR) of

OWR

=

(---M-----C----L----K-----⁄---K----)

1024

where K is the value of the clock divider selected in the

Configuration Register by bits K[3:0]. Note that a value

of K[3:0] = 0000 results in a clock divider setting of 16,

rather than zero.

The RMS voltage (VRMS, V2RMS), RMS current (IRMS,

I2RMS), and active power (Pactive, P2active) are comput-

ed using N instantaneous samples of Vn, In, and Pn re-

spectively, where N is the value in the Cycle Count

Register and is referred to as a “computation cycle”. The

apparent power (S, S2) is the product of VRMS and IRMS.

A computation cycle is derived from the master clock

DS682PP1

17

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