CS5461 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5461

Single Phase Bi-Directional Power/Energy IC

Cirrus Logic 

CS5461

7.5 PulseRateE Register

Address: 6

MSB

LSB

218

217

216

215

214

213

212

211

.....

21

20

2-1

2-2

2-3

2-4

2-5

Default** = 32000.00 Hz

The PulseRateE Register determines the average frequency of the pulses issued on the EOUT output pin. The

register’s smallest valid value is 2-4 but can be in 2-5 increments. A pulserate higher than MCLK/K/8 will result

in a pulse rate setting of MCLK/K/8.

7.6 I, V, P, & PAvg: Instantaneous Current, Voltage, Power, and Average Power (Signed)

Output Register

Address: 7 - 10

MSB

LSB

-(20) 2-1

2-2

2-3

2-4

2-5

2-6

2-7

..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

These signed registers contain the last measured value of I, V, P, and PAVG. The results will be within in the

range of -1.0 ≤ I,V,P,PAvg< 1.0. The value is represented in two's complement notation, with the binary point

place to the right of the MSB (MSB has a negative weighting). These values are 22 bits in length. The two least

significant bits have no meaning, and will always have a value of “0”.

7.7 IRMS, VRMS Unsigned Output Register

Address: 11,12

MSB

LSB

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

..... 2-18 2-19 2-20 2-21 2-22 2-23 2-24

These unsigned registers contain the last values of IRMS and VRMS. The results are in the range of

0.0 ≤ IRMS,VRMS < 1.0. The value is represented in (unsigned) binary notation, with the binary point place to the

left of the MSB. These results are updated after each computation cycle.

7.8 Timebase Calibration Register

Address: 13

MSB

LSB

20

2-1

2-2

2-3

2-4

2-5

2-6

2-7

..... 2-17 2-18 2-19 2-20 2-21 2-22 2-23

Default** = 1.000

This register can be set with a clock frequency error compensation value, to correct for a gain/timing error

caused by the crystal/oscillator tolerance. The value is in the range 0.0 ≤ TBC < 2.0.

DS546F2

35

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