CS5461-IS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5461-IS

Single Phase Bi-Directional Power/Energy IC

Cirrus Logic 

CS5461

6.2 Serial Port Interface

The CS5461’s serial interface consists of four con-

trol lines, which have the following pin-names: CS,

SDI, SDO, and SCLK.

1) CS is the control line which enables access to

the serial port. If the CS pin is tied to logic 0,

the port can function as a three wire interface.

2) SDI is the data signal used to transfer data to the

converter.

3) SDO is the data signal used to transfer output

data from the converter. The SDO output will

be held at high impedance any time CS is at

logic 1.

4) SCLK is the serial bit-clock which controls the

shifting of data to or from the ADC’s serial

port. The CS pin must be held at logic 0 before

SCLK transitions can be recognized by the port

logic. To accommodate opto-isolators SCLK is

designed with a Schmitt-trigger input to allow

an opto-isolator with slower rise and fall times

to directly drive the pin.

6.3 Serial Read and Write

The state machine decodes the command word as it

is received. Data is written to and read from the

CS5461 by using the Register Read/Write opera-

tion. A transfer of data is always initiated by send-

ing the appropriate 8-bit command (MSB first) to

the serial port (SDI pin). Figure 1 illustrates the se-

rial sequence necessary to write to, or read from the

serial port’s buffers.

During a write operation, the serial port will contin-

ue to clock in the data bits (MSB first) on the SDI

pin for the 24 SCLK cycles.

When a read command is initiated, the serial port

will start transferring register content bits serial

(MSB first) on the SDO pin for 8, 16, or 24 SCLK

cycles. Command words instructing a register read

may be terminated at 8-bit boundaries. Also data

register reads allow “command chaining”. This

means the micro-controller can send a new com-

mand while reading register data. The new com-

mand will be acted upon immediately and could

possibly terminate the first register read. For exam-

ple, if only the 16 most significant bits of data from

the first read are required, a second read command

on SDI can be initiated after the first 8 data bits are

read from SDO.

During a read cycle, the SYNC0 command

(NOP) should be strobed on the SDI port while

clocking the data from the SDO port.

6.4 System Initialization

A software or hardware reset can be initiated at any

time. The software reset is initiated by sending the

command 0x80.

A hardware reset is initiated when the RESET pin

is forced low with a minimum pulse width of 50 ns.

The RESET signal is asynchronous, requiring no

MCLKs for the part to detect and store a reset

event. The RESET pin is a Schmitt Trigger input,

which allows it to accept slow rise times and/or

noisy control signals. Once the RESET pin is inac-

tive, the internal reset circuitry remains active for 5

MCLK cycles to insure resetting the synchronous

circuitry in the device. The modulators are held in

reset for 12 MCLK cycles after RESET becomes

inactive. After a hardware or software reset, the in-

ternal registers (some of which drive output pins)

will be reset to their default values on the first

MCLK received after detecting a reset event. The in-

ternal register values are also set to their default val-

ues after initial power-on of the device. The CS5461

will then assume its active state.

6.5 Serial Port Initialization

It is possible for the serial interface to become un-

synchronized, with respect to the SCLK input. If

this occurs, any attempt to clock valid CS5461

commands into the serial interface may result in

unexpected operation. The CS5461’s serial port

must then be re-initialized. To initialize the serial

DS546F2

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