CS5461-IS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5461-IS Datasheet PDF : 45 Pages
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CS5461
4.4.6.4 DC Gain Calibration Sequence
Based on the level of the positive DC calibration
voltage applied across the “+’ and “-” inputs, the
CS5461 determines the DC Gain Register value by
averaging the Instantaneous Register’s output sig-
nal values over one computation cycle (N samples)
and then dividing this average into 1. Therefore, af-
ter the DC gain calibration, the Instantaneous Reg-
ister will read at full-scale whenever the DC level
of the input signal is equal to the level of the DC
calibration signal applied to the inputs during the
DC gain calibration (see Figure 9).
4.4.7 Duration of Calibration Sequence
The value of the Cycle Count Register (N) deter-
mines the number of conversions performed by the
CS5461 during a given calibration sequence. For
DC offset/gain calibrations, the calibration se-
quence takes at least N + 30 conversion cycles to
complete. For AC offset/gain calibrations, the cali-
bration sequence takes at least 6N + 30 A/D con-
Before AC Gain Calibration (Vgain Register = 1)
250 mV
230 mV
Sinewave
INPUT 0 V
SIGNAL
0.9999...
0.92
Instantaneous Voltage
Register Values
-230 mV
-250 mV
-0.92
-1.0000...
VRMS Register = 230/250 x 1/√2 ≈ 0.65054
Before AC Gain Calibration (Vgain Register = 1)
250 mV
230 mV
DC Signal
INPUT 0 V
SIGNAL
0.9999...
0.92
Instantaneous Voltage
Register Values
-250 mV
VRMS Register = 230/250 = 0.92
-1.0000...
After AC Gain Calibration (Vgain Register changed to ~0.9223)
250 mV
Sinewave 230 mV
0.92231
0.84853
INPUT
SIGNAL 0 V
Instantaneous Voltage
Register Values
-230 mV
-250 mV
VRMS Register = 0.6000...
-0.84853
-0.92231
Figure 7. Example of AC Gain Calibration
After AC Gain Calibration (Vgain Register changed to ~0.65217)
250 mV
230 mV
DC Signal
INPUT 0 V
SIGNAL
0.65217
0.6000
Instantaneous Voltage
Register Values
-250 mV
-0.65217
VRMS Register = 0.6000...
Figure 8. Another Example of AC Gain Calibration
In
M o d ula to r
DS546F2
to V*, I*, P*, E* Registers
Filter
++
+
D C Offset*
x
G ain *
1
x
2
X
+
+
-
SINC 2
N
Σ
AC Offset*
÷N
N
2
X
-X
0.6
x
* Denotes readable/writable register
Figure 6. Calibration Data Flow
X
÷N
V RMS*
19
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