CS5461 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5461

Single Phase Bi-Directional Power/Energy IC

Cirrus Logic 

CS5461

power can be multiplied by the time duration of the

computation cycle, to generate a value for the accu-

mulated real energy over the last computation cy-

cle.

3.1.6 RMS Computations

RMS calculations are performed on the instanta-

neous voltage/current data and can be read from the

RMS Voltage Register and the RMS Current Reg-

ister. The results are computed once every compu-

tation cycle. Using N instantaneous current

samples (In), the RMS computations for the current

(and likewise for voltage, using Vn) is performed

using the formula:

RMS =

N -1

Σ In

n=0

N

3.2 Performing Measurements

The CS5461 performs measurements of instanta-

neous voltage, instantaneous current, instantaneous

power at an output word rate (sampling rate) of

(MCLK/K) / 1024. From these instantaneous sam-

ples, average (real) power, IRMS, and VRMS are

computed, using the most recent N instantaneous

samples that were acquired. All of the measure-

ments/results are available as a percentage of full

scale. The signed output format is a two’s comple-

ment format, and the output data words represent a

normalized value between -1 and +1. The un-

signed data in the CS5461 output registers repre-

sent normalized values between 0 and 1. A register

value of 1 represents the maximum possible value.

Note that a value of 1.0 is never actually obtained,

the true maximum register value is [(2^23 - 1) /

(2^23)] = 0.999999880791.

After each A/D conversion, the CRDY bit will be

asserted in the Status Register, and the INT pin will

also become active if the CRDY bit is unmasked

(in the Mask Register). The assertion of the CRDY

bit indicates that new instantaneous samples have

been collected.

The unsigned VRMS, IRMS, and average power cal-

culations are updated every N conversions (which

is known as 1 “computation cycle”) where N is the

value in the Cycle Count Register. At the end of

each computation cycle, the DRDY bit in the Mask

Register will be set, and the INT pin will become

active if the DRDY bit is unmasked.

DRDY is set only after each computation cycle has

completed, whereas the CRDY bit is asserted after

each individual A/D conversion. When these bits

are asserted, they must be cleared by the user be-

fore they can be asserted again. If the Cycle Count

Register value (N) is set to 1, all output calculations

are instantaneous, and DRDY will indicate when

instantaneous calculations are finished, just like the

CRDY bit. For the RMS results to be valid, the Cy-

cle-Count Register must be set to a value greater

than 10.

A computation cycle is derived from the master

clock and its frequency is (MCLK/K)/(1024*N).

Under default conditions with a 4.096 MHz clock

at XIN, instantaneous A/D conversions for voltage,

current, and power are performed at a 4000 Hz rate,

whereas IRMS, VRMS, and energy calculations are

performed at a 1 Hz rate.

3.3 CS5461 Linearity Performance

Avg Power

Range (% of FS) 0.1% - 100%

Linearity

0.1% of

reading

Vrms

1% - 100%

0.1% of

reading

Irms

0.2% - 100%

0.1% of

reading

Table 1. Available range of ±0.1% output linearity,

with default settings in the gain/offset registers.

Table 1 lists the range of input levels (as a percent-

age of full-scale registration in the Average Power,

Irms, and Vrms Registers) over which the output

linearity of the Vrms, Irms and Average Power

Register measurements are guaranteed to be within

DS546F2

15

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