
CS5378
20.2.7 TBSCFG : 0x2A
Figure 49. Test Bit Stream Configuration Register TBSCFG
(MSB) 23
INTP7
R/W
0
22
INTP6
R/W
0
15
14
--
RATE2
R/W
R/W
0
0
7
LOOP
R/W
0
6
RUN
R/W
0
21
INTP5
R/W
0
13
RATE1
R/W
0
5
DDLY5
R/W
0
20
INTP4
R/W
0
12
RATE0
R/W
0
4
DDLY4
R/W
0
19
INTP3
R/W
0
11
TSYNC
R/W
0
3
DDLY3
R/W
0
18
INTP2
R/W
0
10
--
R/W
0
2
DDLY2
R/W
0
17
INTP1
R/W
0
9
--
R/W
0
1
DDLY1
R/W
0
16
INTP0
R/W
0
8
--
R/W
0
(LSB) 0
DDLY0
R/W
0
DF Address: 0x2A
--
Not defined;
read as 0
R
Readable
W
Writable
R/W Readable and
Writable
Bits in bottom rows
are reset condition
Bit definitions:
23:16 INTP[7:0]
Interpolation factor 15 --
reserved
7
0xFF: 256
0xFE: 255
...
0x01: 2
0x00: 1 (use once)
14:12 RATE[2:0] TBSDATA and 6
TBSCLK output
rate.
111: 2.048 MHz
110: 1.024 MHz
101: 512 kHz
100: 256 kHz
011: 128 kHz
010: 64 kHz
001: 32 kHz
000: 4 kHz
LOOP
RUN
Loopback
TBSDATA output
to MDATA inputs
1: Enabled
0: Disabled
Run Test Bit Stream
1: Enabled
0: Disabled
11 TSYNC
10:8 --
Synchronization 5:0 DDLY[5:0] TBSDATA output
1: Sync enabled
0: No sync
delay
0x3F: 63 bits
0x3E: 62 bits
...
0x01: 1 bit
0x00: 0 bits ( no
delay)
reserved
DS639F2
78