CS5351
7 REVISION HISTORY
Release Date
PP2
Sept 2002
F1
Feb 2004
Changes
Preliminary datasheet.
Improve Gain Error specification under Analog Characteristics.
Specify Full-scale Input Voltage in terms of VA under Analog Characteristics.
Update Differential Input Impedance under Analog Characteristics.
Increase maximum Power-Supply Current, IA, under DC Electrical Characteristics.
Reduce maximum Power Consumption under DC Electrical Characteristics.
Update FILT+ Output Impedance specification under DC Electrical Characteristics.
Extend maximum Fs in Single-Speed Mode to 51 kHz.
Extend maximum Fs in Double-Speed Mode to 102 kHz.
Extend maximum Fs in Quad-Speed Mode to 204 kHz.
Decrease maximum SCLK falling to LRCK edge specification in Quad-Speed Mode.
Replace minimum MCLK high/low timing specifications with duty cycle specification.
Replace minimum SCLK high/low timing specifications with duty cycle specification.
Replace recommended analog input buffer with new input buffer topology.
Table 4. Revision History
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com
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