3. TYPICAL CONNECTION DIAGRAM
3.3V to 5V
3.3V to 5V
+
1 µF
+
1 µF
0.1 µF
0.1 µF
**
5.1Ω
0.1 µF
0.1 µF
+
1 µF
CS5340
1.8 V to 5V
***+
1µF
VA
VD
FILT+
0.1 µF
REFGND
+ 1µF
0.1 µF
VQ
CS5340
VL
RST
M0
M1
Analog Input Buffer
Figure 21
AINL
AINR
A/D CONVERTER
VL or GND
10kΩ *
SDOUT
Power Down
and Mode
Settings
Audio Data
Processor
GND
MCLK
LRCK
SCLK
Timing Logic
and Clock
* Pull-up to VL for I2S
Pull-down to GND for LJ
** Resistor may only be
used if VD is derived from
VA. If used, do not drive
any other logic from VD
*** Capacitor value affects
low frequency distortion
performance as described
in Section 4.8
14
DS601F1