CS5338 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5338 Datasheet PDF : 34 Pages
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CDB5336,8,9
VD+
R8 20 k
13
SMODE
15 SCLK
SCLK
17 FSYNC
FSYNC
14 L/R
L/R
16 SDATA
SDATA
SDATA
VD+
4
5 U8B 6
9 10
U8C 74HC08
8
SDATA
1
A-to-B
Enable
13 B-to-A
Enable
14
VCC
11
B1
7
U9 GND
10 B2
74HC243
3
A1
9 B3
4
A2
VD+
0.1 uF
C20
6
A4 B4
5
A3
SCLK
FSYNC
L/R
R9
8 R10
20 k
20 k
U7B
3
4
5336/38
CS8402
Pin 6
5337/39
P4
Pin 11
U4, U5
595’s
Figure 5. Serial Output Interface
on the rising edge of SCLK and shifted into the
16-bit shift register formed by U4 and U5 on
SCLK’s falling edge. After all data bits for the
selected channel have been shifted into U4 and
U5 the data is latched onto P1 by a delayed ver-
sion of FSYNC.
P5 selects the channel whose output data will be
converted to parallel form and presented on P1.
With P5 in the "B" (both) position, parallel data
from one channel will be presented first with
data from the other channel presented sub-
sequently. In the "L" (left) position, only left
channel conversions will be presented, while in
the "R" (right) position only right channel con-
versions are presented.
Two interface mechanisms are provided for read-
ing the data from this port. With the first, the
edges of L/R may be used to clock the parallel
data into the digital signal processor. (Set jumper
P2 into the L/R position.) Alternatively, a hand-
shake protocol implemented with DACK and
DRDY may be used to transfer data to the signal
processor. (Set jumper P2 to the DRDY posi-
tion.) The fall of DRDY informs the digital
signal processor that a new data word is avail-
able. The processor then reads the port and
acknowledges the transfer by asserting DACK.
Note that DRDY will not be asserted again un-
less DACK is momentarily brought high
although new data will continue to be latched
onto the port.
Digital Audio Standard Interface
Included on the evaluation board is a CS8402
Digital Audio Line Driver. This device can im-
plement AES/EBU, S/PDIF and EIAJ CP-340
interface standards. Figure 4 shows the sche-
matic for the CS8402. P3 allows the C, U and V
bits to be driven from external logic using the
CBL output for block synchronization. SW2 pro-
vides 8 DIP switches to select various modes
and bits for the CS8402. Table 3 lists the settings
for the professional mode which is the default
setting for the evaluation board from the factory.
The third switch selects between professional
DS23DB5
3-65
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