CS4922-CL View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS4922-CL Datasheet PDF : 33 Pages
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CS4922
Digital-to-Analog Converter
AOUTL, AOUTR - Analog Outputs, Left and Right Channels, PINS 38, 39.
These DAC outputs are centered at approximately 2.2V. An external filter is required to
diminish out-of-band noise. See Typical Connection Diagram, Figure 1.
AOUTM - Mono Analog Output, PIN 37.
Mono is the summation of AOUTL and AOUTR. Mono output is 180° out-of-phase with the
sum of AOUTL and AOUTR. Mono is centered at approximately 2.2V. An external filter is
required to diminish out-of-band noise. See Typical Connection Diagram, Figure 1.
Serial Audio Port
FSYNC - Frame Synchronization Clock Input, PIN 23.
When SCLK and SDATA are used for delivering compressed data to the CS4922 (e.g. the
MPEG application code), the FSYNC pin should be tied to the +5V supply. When SCLK and
SDATA are used for delivering PCM data (e.g. the G.729A application code), FSYNC
transitions delineate left and right audio data, or the start of a data frame.
SCLK - Serial Clock Input, PIN 22.
SCLK is used to clock the serial audio data on SDATA into the device. The active edge of
SCLK is determined by the application code running on the CS4922.
SDATA - Serial Audio Data Input, PIN 21.
SDATA is an audio data input pin for the CS4922. The data is clocked in on the active edge
of SCLK.
Digital Audio Transmitter
TX - Transmitter Output, PIN 5.
Biphase mark encoded data is output at logic levels from the TX pin. This output typically
connects to the input of an RS-422 or optical transmitter. With additional external circuitry, the
port can support either AES/EBU or S/PDIF formats.
Clock Manager
CLKOUT - Clock Output, PIN 24.
CLKOUT can be used to synchronize peripheral devices such as a micro controller or an audio
source. The clock frequency is determined by a divide by Q in the clock manager. The
maximum CLKOUT frequency is the maximum DSP frequency divided by 2.
ALTCLK - Clock Input, PIN 28.
When EXTCK is high, ALTCLK is an input for an externally generated clock. This clock
directly becomes the DSP clock and the clock frequency should be 512Fs or 768Fs.
28
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