CS4922 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS4922

MPEG/G.729A Audio Decoder System

Cirrus Logic 

CS4922

3 THEORY OF OPERATION

3.1 Introduction

The CS4922 is a complete audio subsystem on a

chip. It consists of a general-purpose Digital Signal

Processor (DSP), and a number of supplementary

analog and digital blocks. These supplementary

blocks include a PLL clock multiplier, a serial au-

dio input port, an auxiliary serial audio port, a CD

quality stereo Digital-to-Analog Converter (DAC),

an AES/EBU - S/PDIF compatible digital audio

transmitter, and a serial control port. Figure 6

shows a typical connection diagram for the CS4922

in which a micro controller is used for loading the

program code.

The CS4922 is RAM based audio decoder that can

be used to process compressed digital audio sig-

nals. Serial audio data broadcast on networks such

as cable TV, direct broadcast satellite TV, or the

telephone system can be decompressed and con-

verted to standard analog and digital signals. A

wide variety of standard and proprietary decom-

pression algorithms can be supported.

CS4922 application code is available which per-

forms industry standard MPEG 1 and 2, layers I

and II. Application code is also available for

G.729A decode.

The DSP has a 24-bit fixed point data path, 5K

words of program RAM, and 3K words of data

RAM. The execution unit includes a 48-bit accu-

mulator. The DSP can provide up to 12 MIPS.

Either compressed digital audio data or PCM data

can be delivered.

For analog reproduction of the digital input, a ste-

reo DAC using delta-sigma architecture is built-in.

Switched-capacitor filters perform most of the re-

construction process. Only a simple external pas-

sive filter is needed to complete reconstruction.

In addition to the analog output, an AES/EBU -

S/PDIF compatible output is provided. This allows

the designer the flexibility of transmitting the audio

data in a standard digital format to an external sys-

tem.

To facilitate the downloading of DSP code to the

CS4922, a serial control port, communicating in ei-

ther I2C® or SPI format, is used. This port may also

be used during run time to issue control commands

to the DSP.

4 PERIPHERALS

Six on-chip peripherals make the audio decoder

ideal for decoding broadcast digital audio signals.

It has a PLL clock manager, a CD quality DAC, a

digital audio transmitter, a three pin serial port for

audio data input, a serial bi-directional auxiliary

port for digital audio data, and an SPI/I2C port for

serial control information. Each peripheral has I/O

mapped data, control, and status registers. Many

peripherals can also generate interrupts.

4.1 Clock Manager

The clock manager is primarily a clock multiplier

circuit that takes a reference frequency of 27 MHz

on CLKIN which is used for deriving internal

clocking. At the heart of the clock manager circuit

is a PLL (Phase-Locked Loop) circuit. The PLL is

configured by software to produce the appropriate

DSP Clock for the desired sample rate. All other in-

ternal clocks required for the DAC and other pe-

ripherals are derived from this root clock.

The PLL’s internal VCO requires a capacitor to be

connected to the FLT pin (pin 31). The typical val-

ue of the FLT capacitor is 0.47 µf, which is suffi-

cient for all allowable CLKIN input frequencies. It

must be stressed that the best analog performance

can only be achieved by placing the capacitor as

close as possible to the FLT pin and that the proper

layout precautions be taken to avoid noise coupling

onto the FLT pin.

The CLKOUT pin is a divided version of the DSP

clock. A diagram of the CLKOUT generation cir-

cuit is shown in Figure 7.

15

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