CS4525 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS4525

30 W Digital Audio Amplifier with Integrated ADC

Cirrus Logic 

9.8 Tone Control (Address 08h)

7

Treble3

6

Treble2

5

Treble1

4

Treble0

3

Bass3

2

Bass2

CS4525

1

Bass1

0

Bass0

9.8.1

Treble Gain Level (Treb[3:0])

Default = 1000

Function:

Sets the gain/attenuation level of the treble shelving filter.The level can be adjusted in 1.5 dB steps from

+12.0 to -10.5 dB.

Treb[3:0] Setting

Treble Shelving Filter Gain/Attenuation

0000 .................................... +12 dB

0001 .................................... +10.5 dB

.....................................

1000 .................................... 0 dB

.....................................

1110 ..................................... -9.0 dB

1111 ..................................... -10.5 dB

9.8.2

Bass Gain Level (Bass[3:0])

Default = 1000

Function:

Sets the gain/attenuation level of the bass shelving filter. The level can be adjusted in 1.5 dB steps from

+12.0 to -10.5 dB.

Bass[3:0] Setting

Bass Shelving Filter Gain/Attenuation

0000 .................................... +12 dB

0001 .................................... +10.5 dB

.....................................

1000 .................................... 0 dB

.....................................

1110 ..................................... -9.0 dB

1111 ..................................... -10.5 dB

9.9 2.1 Bass Manager/Parametric EQ Control (Address 09h)

7

Freeze

6

HiZPSig

5

BassMgr2

4

BassMgr1

3

BassMgr0

2

Reserved

1

EnChBPEq

0

EnChAPEq

9.9.1

Freeze Controls (Freeze)

Default = 0

Function:

This function will freeze the previous output of, and allow modifications to be made to the master volume

control (address 57h), channel X volume control (address 58h - 5Ah), and bi-quad coefficient registers for

channel A, and channel B (address 0Ah - 54h) without the changes taking effect until the Freeze bit is

disabled. To make multiple changes in these control port registers take effect simultaneously, enable the

Freeze bit, make all register changes, then disable the Freeze bit.

Freeze Setting

Register Freeze State

0 .......................................... Register freeze disabled.

1 .......................................... Register freeze enabled.

78

DS726PP1

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