CS4525(2008) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS4525 Datasheet PDF : 98 Pages
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CS4525
only be changed while all modulators and associated logic are in the power-down state (the PDnAll bit is
set). Attempts to write these bits while the PDnAll bit is cleared will be ignored. See “PWM Channel Delay”
on page 55 for more information.
OutputDly[3:0] Setting Output Delay in Input Clock Source Cycles
0000 .................................... 0 - No Delay
0001 .................................... 1
0010 .................................... 2
....................................
1000 .................................... 8
....................................
1111 ..................................... 15 - Max Delay
9.5 Foldback and Ramp Configuration (Address 05h)
7
SelectVP
6
EnTherm
5
LockAdj
4
AttackDly1
3
AttackDly0
2
EnFloor
1
0
RmpSpeed1 RmpSpeed0
9.5.1
Select VP Level (SelectVP)
Default = 1
Function:
Adjusts the PWM modulation index to maximize output power for applications with a nominal VP voltage
of less than or equal to 14 V. This bit must remain set for applications with a nominal VP voltage greater
than 14 V.
SelectVP Setting
Selected VP Level
0 .......................................... VP ≤ 14 Volts
1 .......................................... VP > 14 Volts.
9.5.2
Enable Thermal Foldback (EnTherm)
Default = 0
Function:
Enables the thermal foldback feature. See “Thermal Foldback” on page 40 for more information.
EnTherm Setting
Thermal Foldback State
0 .......................................... Disabled.
1 .......................................... Enabled.
9.5.3
Lock Foldback Adjust (LockAdj)
Default = 0
Function:
Controls the operation of the foldback lock adjustment feature. See “Thermal Foldback” on page 40 for
more information.
LockAdj Setting
Foldback Adjustment Lock State
0 .......................................... Attenuation lock disabled.
1 .......................................... Attenuation lock enabled.
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DS726PP3
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