CS4614-CM View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS4614-CM Datasheet PDF : 24 Pages
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CS4614
CrystalClear™ SoundFusion™ PCI Audio Accelerator
and Invalidate, I/O Read, I/O Write, Interrupt Ac-
knowledge, Special Cycles, and Dual Address Cy-
cle transactions are not generated.
The PCI bus transactions supported by the CS4614
device are summarized in Table 1. Note that no
Target Abort conditions are signalled by the de-
vice. Byte, Word, and Doubleword transfers are
supported for Configuration Space accesses. Only
Doubleword transfers are supported for Register or
Memory area accesses. Bursting is not supported
for host-initiated transfers to/from the CS4614 in-
ternal register space, RAM memory space, or PCI
configuration space (disconnect after first phase of
transaction is completed).
Configuration Space
The content and format of the PCI Configuration
Space is given in Table 2.
Initiator
Target
Type
PCI Dir
Host
Registers (BA0)
Mem Write In
Host
Registers (BA0)
Mem Read Out
Host
Memories (BA1)
Mem Write In
Host
Memories (BA1)
Mem Read Out
Host
Config Space 1
Config Write In
Host
Config Space 1
Config Read Out
DMA
Host System
Mem Write Out
DMA
Host System
Mem Read In
Table 1. PCI Interface Transaction Summary
Byte 3
Byte 2
Byte 1
Byte 0
Device ID: R/O, 6003h
Vendor ID: R/O, 1013h
Status Register, bits 15-0:
Bit 15 Detected Parity Error: Error Bit
Bit 14 Signalled SERR: Error Bit
Bit 13 Received Master Abort: Error Bit
Bit 12 Received Target Abort: Error Bit
Bit 11 Signalled Target Abort: Error Bit
Bit 10-9 DEVSEL Timing: R/O, 01b (medium)
Bit 8 Data Parity Error Detected: Error Bit
Bit 7 Fast Back to Back Capable: R/O 0
Bit 6 User Definable Features: R/O 0
Bit 5 66MHz Bus: R/O 0
Bit 4 New Capabilities: R/O 1
Bit 3-0Reserved: R/O 0000
Reset Status State: 0210h
Write of 1 to any error bit position clears it.
Command Register, bits 15-0:
Bit 15-10: Reserved, R/O 0
Bit 9 Fast B2B Enable: R/O 0
Bit 8 SERR Enable: R/W, default 0
Bit 7 Wait Control: R/O 0
Bit 6 Parity Error Response: R/W, default 0
Bit 5 VGA Palette Snoop: R/O 0
Bit 4 MWI Enable: R/O 0
Bit 3 Special Cycles: R/O 0
Bit 2 Bus Master Enable: R/W, default 0
Bit 1 Memory Space Enable: R/W, default 0
Bit 0 IO Space Enable: R/O 0
Table 2. PCI Configuration Space
Offset
00h
04h
12
CIRRUS LOGIC PRELIMINARY PRODUCT BULLETIN JUNE 30, 5:03 PM
DS292PP3
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