CS4392
SWITCHING SPECIFICATIONS - DSD INTERFACE (Logic 0 = AGND; Logic 1 = VL)
MCLK Duty Cycle
Parameter
DSD_SCLK Pulse Width Low
DSD_SCLK Pulse Width High
DSD_SCLK Period
DSD_L or DSD_R valid to DSD_SCLK rising setup time
DSD_SCLK rising to DSD_L or DSD_R hold time
Symbol Min
40
tsclkl
20
tsclkh
20
tsclkw
20
tsdlrs
20
tsdh
20
Max
60
-
-
-
-
-
Unit
%
ns
ns
ns
ns
ns
DSD_SCLK
DSD_L, DSD_R
t sclkh
t sclkl
t sdlrs t sdh
Figure 37. Direct Stream Digital - Serial Audio Input Timing
DS459PP2
33