CS4391A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS4391A

24-Bit, 192 kHz Stereo DAC with Volume Control

Cirrus Logic 

CS4391A

7. APPLICATIONS

7.1 Recommended Power-up

Sequence for Hardware Mode

1) Hold RST low until the power supplies, master,

and left/right clocks are stable.

2) Bring RST high.

7.2 Recommended Power-up

Sequence and Access to Control

Port Mode

1) Hold RST low until the power supply, master,

and left/right clocks are stable. In this state, the

control port is reset to its default settings and

CMOUT will remain low.

2) Bring RST high. The device will remain in a

low power state with CMOUT low and the con-

trol port is accessible.

3) Write 30h to register 5 within 10 ms cycles fol-

lowing the release of RST.

4) The desired register settings can be loaded

while keeping the PDN bit set to 1.

5) Set the PDN bit to 0 which will initiate the pow-

er-up sequence which requires approximately

10 µS.

7.3 Analog Output and Filtering

The application note “Design Notes for a 2-Pole

Filter with Differential Input” discusses the second-

order Butterworth filter and differential to single-

ended converter which was implemented on the

CS4391A evaluation board, CDB4391A. The

CS4391A filter, as seen in Figure 14, is a linear

phase design and does not include phase or ampli-

tude compensation for an external filter. Therefore,

the DAC system phase and amplitude response will

be dependent on the external analog circuitry.

C42

AOUTA-

C43

AOUTA+

10UF

10UF

R24

R26

AMUTEC

C7

2700PF

COG

GND

R28

5.62K

C6 560PF

COG

VCC

C49

.1UF

5.62K

5.62K

R17

R18

C14

2700PF

COG

GND

R15

5.62K

1.18K

1.18K

8

V+ U11 GND

2

-

1

3

+

MC33078D

C5

V- 4

560PF

COG

C48

GND

VEE

.1UF

GND

GND

VA+3/+5

2

MMUN2111LT1

1

Q3

3

Q4

1

MMUN2211LT1

3

R25

2K

2

GND

R20

560

J3

CON_RCA_RA

1

R5

2

47K

3

4 NC AOUTA

GND

GND

Q1

2SC2878 2

3

1

GND

Figure 15. CS4391A Output Filter

DS600PP3

33

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