8. REGISTER DESCRIPTION
** All register access is R/W unless specified otherwise**
CS4350
8.1 Chip ID - Register 01h
7
PART4
1
6
PART3
1
5
PART2
1
4
PART1
1
3
PART0
0
2
REV2
-
1
REV1
-
0
REV0
-
Function:
This register is Read-Only. Bits 7 through 3 are the part number ID which is 11110b and the remaining Bits
(2 through 0) are for the chip revision (Rev. A0 = 000)
8.2 Mode Control - Register 02h
7
Reserved
0
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
DEM1
0
2
DEM0
0
1
FM1
0
0
FM0
0
8.2.1
Digital Interface Format (DIF[2:0]) Bits 6-4
Function:
These bits select the interface format for the serial audio input.
The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital
Interface Format and the options are detailed in Figures 8-10.
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
Description
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 16-bit data
Right-Justified, 24-bit data
TDM slot 0
TDM slot 1
TDM slot 2
TDM slot 3
Table 4. Digital Interface Formats
Format
0 (Default)
1
2
3
4
5
6
7
Figure
8
9
10
10
12
12
12
12
8.2.2
De-Emphasis Control (DEM[1:0]) Bits 3-2
Default = 0
00 - No De-emphasis
01 - 44.1 kHz De-emphasis
10 - 48 kHz De-emphasis
11 - 32 kHz De-emphasis
Gain
dB
0dB
T1=50 µs
Function:
-10dB
T2 = 15 µs
Selects the appropriate digital filter to maintain the standard
15 µs/50 µs digital de-emphasis filter response at 32, 44.1
or 48 kHz sample rates. (See Figure 18)
Note: De-emphasis is only available in Single-Speed
Mode
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 18. De-Emphasis Curve
28
DS691A3