CS5364-CQZ(2007) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5364-CQZ Datasheet PDF : 41 Pages
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CS5364
Bits[5:4] MDIV[1:0] Each bit selects an XTI divider. When either bit is low, an XTI divide-by-1 function is
selected. When either bit is HIGH, an XTI divide-by-2 function is selected. With both bits HIGH, XTI is divid-
ed by 4.
The table below shows the composite XTI division using both CLKMODE and MDIV[1:0].
CLKMODE,MDIV[1],MDIV[0]
000
100
001 or 010
101 or 110
011
111
DESCRIPTION
Divide-by-1
Divide-by-1.5
Divide-by-2
Divide-by-3
Divide-by-4
Reserved
Bits[3:2] DIF[1:0] Determine which data format the serial audio interface is using to clock-out data.
DIF[1:0]
0x00 Left-Justified format
0x01 I²S format
0x02 TDM
0x03 Reserved
Bits[1:0] MODE[1:0] This bit field determines the device sample rate range and whether it is operating as
an audio clocking Master or Slave.
MODE[1:0]
0x00 Single-Speed Mode Master
0x01 Double-Speed Mode Master
0x02 Quad-Speed Mode Master
0x03 Slave Mode all speeds
5.4 02h (OVFL) Overflow Status Register
R/W
7
6
5
4
R
RESERVED RESERVED RESERVED RESERVED
3
OVFL4
2
OVFL3
1
OVFL2
0
OVFL1
Default: 0xFF, no overflows have occurred.
Note: This register interacts with Register 03h, the Overflow Mask Register.
The Overflow Status Register is used to indicate an individual overflow in a channel. If an overflow condition
on any channel is detected, the corresponding bit in this register is asserted (low) in addition to the open
drain active low OVFL pin going low. Each overflow status bit is sticky and is cleared only when read, pro-
viding full interrupt capability.
5.5 03h (OVFM) Overflow Mask Register
R/W
7
6
5
4
3
R/W RESERVED RESERVED RESERVED RESERVED OVFM4
2
OVFM3
1
OVFM2
0
OVFM1
Default: 0xFF, all overflow interrupts enabled.
The Overflow Mask Register is used to allow or prevent individual channel overflow events from creating
activity on the OVFL pin. When a particular bit is set low in the Mask register, the corresponding overflow
bit in the Overflow Status register is prevented from causing any activity on the OVFL pin.
DS625F2
33
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