CS5345 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5345 Datasheet PDF : 41 Pages
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CS5345
6.8.2
PGASoft
0
0
1
1
PGAZeroCross
0
1
0
1
Mode
Changes to affect immediately
Zero Cross enabled
Soft Ramp enabled
Soft Ramp and Zero Cross enabled (default)
Table 11. PGA Soft Cross or Zero Cross Mode Selection
Analog Input Selection (Bits 2:0)
Function:
These bits are used to select the input source for the PGA and ADC. Please see Table 12.
Sel2
0
0
0
0
1
1
1
1
Sel1
0
0
1
1
0
0
1
1
Sel0
0
1
0
1
0
1
0
1
PGA/ADC Input
Microphone-Level Inputs (+32 dB Gain Enabled)
Line-Level Input Pair 1
Line-Level Input Pair 2
Line-Level Input Pair 3
Line-Level Input Pair 4
Line-Level Input Pair 5
Line-Level Input Pair 6
Reserved
Table 12. Analog Input Multiplexer Selection
6.9 Active Level Control - Address 0Ch
7
Reserved
6
Reserved
5
Reserved
4
Reserved
6.9.1 Active High/Low (Bit 0)
3
Reserved
2
Reserved
1
Reserved
0
Active_H/L
Function:
When this bit is set, the INT pin functions as an active high CMOS driver.
When this bit is cleared, the INT pin functions as an active low open drain driver and will require an exter-
nal pull-up resistor for proper operation.
6.10 Interrupt Status - Address 0Dh
7
6
5
4
3
2
1
Reserved
Reserved
Reserved
Reserved
ClkErr
Reserved
Ovfl
0
Undrfl
For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since
the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last
reading of the register. Status bits that are masked off in the associated mask register will always be ‘0’ in
this register. This register defaults to 00h.
DS658F2
35
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