CS5345-CQZ(2004) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5345-CQZ
(Rev.:2004)

105 dB, 24-Bit, 192 kHz Stereo Audio ADC

Cirrus Logic 

CS5345

6.4.1 Master Clock Dividers (Bits 6:4)

Function:

Sets the frequency of the supplied MCLK signal. See Table 7 below for the appropriate settings.

Table 7. MCLK Frequency

MCLK Divider

÷1

÷ 1.5

÷2

÷3

÷4

Reserved

Reserved

MCLK Freq2

0

0

0

0

1

1

1

MCLK Freq1

0

0

1

1

0

0

1

MCLK Freq0

0

1

0

1

0

1

x

6.5 PGAOut Control - Address 06h

7

Reserved

6

PGAOut

5

Reserved

4

Reserved

3

Reserved

2

Reserved

1

Reserved

0

Reserved

6.5.1 PGAOut Source Select (Bit 6)

Function:

This bit is used to configure the PGAOut pins to be either high impedance or PGA outputs. Refer to

Table 8 below.

Table 8. PGAOut Source Selection

PGAOut

0

1

PGAOutA & PGAOutB

High Impedance

PGA Output

6.6 Channel A PGA Control - Address 07h

7

Reserved

6

Reserved

5

Gain5

4

Gain4

3

Gain3

6.6.1 Channel A PGA Gain (Bits 5:0)

Function:

See “Channel B PGA Gain (Bits 5:0)” on page 31.

6.7 Channel B PGA Control - Address 08h

2

Gain2

1

Gain1

0

Gain0

7

Reserved

6

Reserved

5

Gain5

4

Gain4

6.7.1 Channel B PGA Gain (Bits 5:0)

3

Gain3

2

Gain2

1

Gain1

0

Gain0

Function:

Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to

+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.

Register settings outside of the ±12 dB range are reserved and must not be used. See Table 9 for

31

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