CS42L51(2005) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS42L51
(Rev.:2005)

Low Power, Stereo CODEC with Headphone Amp

Cirrus Logic 

CS42L51

Limiter Soft Ramp Disable (LIM_SRDIS)

Default: 0

0 - Off

1 - On

Function:

Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated

by the soft ramp setting. NOTE: This bit is ignored when the zero-cross function is enabled (i.e. when

DAC_SZC[1:0] = ‘01’b or ‘11’b.)

Limiter Zero Cross Disable (LIM_ZCDIS)

Default: 0

0 - Off

1 - On

Function:

Overrides the DAC_SZC setting. When this bit is set, the Limiter attack & release rate will not be dictated

by the zero cross setting.

6.21 Limiter Release Rate Register (Address 1Ah)

7

LIMIT_EN

6

LIMIT_ALL

5

RRATE5

4

RRATE4

3

RRATE3

2

RRATE2

1

RRATE1

0

RRATE0

NOTE: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.

Peak Detect and Limiter Enable (LIMIT_EN)

Default: 0

0 - Disabled

1 - Enabled

Function:

Limits the maximum signal amplitude to prevent clipping when this function is enabled. Peak Signal Limiting

is performed by digital attenuation. NOTE: When the limiter is enabled the AOUT Volume is automatically

controlled and should not be adjusted manually. Alternative volume control may be realized using the

PCMMIXx_VOL[6:0] bits.

Peak Signal Limit All Channels (LIMIT_ALL)

Default: 1

0 - Individual Channel

1 - Both channel A & B

Function:

When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the spe-

cific channel indicating clipping. The other channels will not be affected.

When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on both

channels in response to any single channel indicating clipping.

66

DS679A2

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