CS42418-DQZ(2004) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS42418-DQZ Datasheet PDF : 67 Pages
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CS42418
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C FORMAT (For CQ, TA
= -10 to +70° C; For DQ, TA = -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic
0 = DGND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
SCL Clock Frequency
fscl
-
RST Rising Edge to Start
tirs
500
Bus Free Time Between Transmissions
tbuf
4.7
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
Clock Low time
tlow
4.7
Clock High Time
thigh
4.0
Setup Time for Repeated Start Condition
tsust
4.7
SDA Hold Time from SCL Falling
(Note 16) thdd
0
SDA Setup time to SCL Rising
tsud
250
Rise Time of SCL and SDA
trc
-
Fall Time SCL and SDA
tfc
-
Setup Time for Stop Condition
tsusp
4.7
Acknowledge Delay from SCL Falling
(Note 17)
tack
-
Max
Unit
100
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
1
µs
300
ns
-
µs
(Note 18)
ns
Notes: 16.
17.
18.
Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
2---5---6--1---×5-----F---s- for Single-Speed Mode, 1---2---8--1---×5-----F---s- for Double-Speed Mode, 6---4----1-×--5---F---s- for Quad-Speed Mode
RST
t irs
Stop
S t a rt
SDA
SCL
t buf
t hdst
t high
t
low
t
hdd
t sud t ack
R epe ate d
Start t rd
t hdst
Stop
t fd
t fc
t susp
t sust
t rc
Figure 58. Control Port Timing - I2C Format
62
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