CS42416-DQZR View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS42416-DQZR

110 dB, 192 kHz 6-Ch Codec with PLL

Cirrus Logic 

CS42416

6.4.2

ADC FUNCTIONAL MODE (ADC_FMX)

Default = 00

00 - Single-Speed Mode (4 to 50 kHz sample rates)

01 - Double-Speed Mode (50 to 100 kHz sample rates)

10 - Quad-Speed Mode (100 to 192 kHz sample rates)

11 - Reserved

Function:

Selects the required range of sample rates for the ADC serial port (ADC_SP). These bits must be set

to the corresponding sample rate range when the ADC_SP is in Master or Slave Mode.

6.4.3 ADC CLOCK SOURCE SELECT (ADC_CLK SEL)

Default = 0

0 - ADC_SDOUT clocked from the DAC_SP.

1 - ADC_SDOUT clocked from the ADC_SP.

Function:

Selects the desired clocks for the ADC serial output.

6.4.4 DAC DE-EMPHASIS CONTROL (DAC_DEM)

Default = 0

Function:

Enables the digital filter to maintain the standard 15µs/50µs digital de-emphasis filter response at the

auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless

of this register setting, at any other sample rate. If the FRC_PLL_LK bit is set to a ‘1’b, the auto-detect

sample rate feature is disabled. To apply the correct de-emphasis filter, use the DE-EMPH bits in the

Interrupt Control (address 1Eh) register to set the appropriate sample rate.

DAC_DEM

reg03h[1]

0

1

1

FRC_PLL_LK

reg06h[0]

X

0

1

DE-EMPH[1:0]

reg1Eh[5:4]

XX

XX

00

01

10

11

Table 5. DAC De-Emphasis

De-Emphasis

Mode

No De-Emphasis

Auto-Detect Fs

Reserved

32 kHz

44.1 kHz

48 kHz

44

DS602F1

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