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C8051F98X View Datasheet(PDF) - Silicon Laboratories

Part Name
Description
MFG CO.
C8051F98X Datasheet PDF : 322 Pages
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C8051F99x-C8051F98x
SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time
Bit
7
6
5
4
3
2
1
0
Name AD0LPM
AD0PWR[3:0]
Type R/W
R
R
R
R/W
Reset
0
0
0
0
1
1
1
1
SFR Page = All; SFR Address = 0xBB
Bit Name
Function
7
AD0LPM ADC0 Low Power Mode Enable.
Enables Low Power Mode Operation.
0: Low Power Mode disabled.
1: Low Power Mode enabled.
6:4 Unused Read = 0000b; Write = Don’t Care.
3:0 AD0PWR[3:0] ADC0 Burst Mode Power-Up Time.
Sets the time delay required for ADC0 to power up from a low power state.
For BURSTEN = 0:
ADC0 power state controlled by AD0EN.
For BURSTEN = 1 and AD0EN = 1:
ADC0 remains enabled and does not enter a low power state after
all conversions are complete.
Conversions can begin immediately following the start-of-conversion signal.
For BURSTEN = 1 and AD0EN = 0:
ADC0 enters a low power state after all conversions are complete.
Conversions can begin a programmed delay after the start-of-conversion signal.
The ADC0 Burst Mode Power-Up time is programmed according to the following
equation:
AD0PWR = T----s---t--a---r---t--u---p-- – 1
or
400ns
Tstartup = AD0PWR + 1400ns
Note: Setting AD0PWR to 0x04 provides a typical tracking time of 2 us for the first sample
taken after the start of conversion.
Rev. 1.0
75

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