C8051F93X-C8051F92X View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F93X-C8051F92X

Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU

Silicon Laboratories 

C8051F93x-C8051F92x

Table 22.6. SMBus Status Decoding With Hardware ACK Generation Enabled (EHACK = 1)

Values Read

Values to

Write

Current SMbus State

Typical Response Options

1110

0

0

X

A master START was gener-

ated.

Load slave address + R/W into

SMB0DAT.

0 0 X 1100

A master data or address byte Set STA to restart transfer.

0 0 0 was transmitted; NACK

received.

Abort transfer.

1 0 X 1110

01X -

Load next data byte into

SMB0DAT.

0 0 X 1100

End transfer with STOP.

01X -

1100

0

0

1

A master data or address byte

was transmitted; ACK

End transfer with STOP and start

another transfer.

1

1

X

-

received.

Send repeated START.

1 0 X 1110

Switch to Master Receiver Mode

(clear SI without writing new data

to SMB0DAT). Set ACK for initial

0

0

1

1000

data byte.

Set ACK for next data byte;

Read SMB0DAT.

0 0 1 1000

0

0

1

A master data byte was

received; ACK sent.

Set NACK to indicate next data

byte as the last data byte;

Read SMB0DAT.

Initiate repeated START.

0 0 0 1000

1 0 0 1110

1000

Switch to Master Transmitter

Mode (write to SMB0DAT before 0 0 X 1100

clearing SI).

Read SMB0DAT; send STOP. 0 1 0 -

A master data byte was

0 0 0 received; NACK sent (last

byte).

Read SMB0DAT; Send STOP

followed by START.

1 1 0 1110

Initiate repeated START.

1 0 0 1110

Switch to Master Transmitter

Mode (write to SMB0DAT before 0 0 X 1100

clearing SI).

258

Rev. 1.3

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