C8051F93X-C8051F92X View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F93X-C8051F92X

Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU

Silicon Laboratories 

C8051F93x-C8051F92x

22.1. Supporting Documents

It is assumed the reader is familiar with or has access to the following supporting documents:

1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.

2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor.

3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.

22.2. SMBus Configuration

Figure 22.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage

between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-

directional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply

voltage through a pullup resistor or similar circuit. Every device connected to the bus must have an open-

drain or open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive

state) when the bus is free. The maximum number of devices on the bus is limited only by the requirement

that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively.

VDD = 5 V

VDD = 3 V

VDD = 5 V

VDD = 3 V

Master

Device

Slave

Device 1

Slave

Device 2

SDA

SCL

Figure 22.2. Typical SMBus Configuration

Rev. 1.3

239

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