C8051F93X-C8051F92X View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F93X-C8051F92X

Single/Dual Battery, 0.9–3.6 V, 64/32 kB, SmaRTClock, 10-Bit ADC MCU

Silicon Laboratories 

C8051F93x-C8051F92x

19. Clocking Sources

C8051F93x-C8051F92x devices include a programmable precision internal oscillator, an external oscillator

drive circuit, a low power internal oscillator, and a SmaRTClock real time clock oscillator. The precision

internal oscillator can be enabled/disabled and calibrated using the OSCICN and OSCICL registers, as

shown in Figure 19.1. The external oscillator can be configured using the OSCXCN register. The low

power internal oscillator is automatically enabled and disabled when selected and deselected as a clock

source. SmaRTClock operation is described in the SmaRTClock oscillator chapter.

The system clock (SYSCLK) can be derived from the precision internal oscillator, external oscillator, low

power internal oscillator, or SmaRTClock oscillator. The global clock divider can generate a system clock

that is 1, 2, 4, 8, 16, 32, 64, or 128 times slower that the selected input clock source. Oscillator electrical

specifications can be found in the Electrical Specifications Chapter.

Option 2

VDD

Option 3

XTAL2

XTAL2

Option 1

XTAL1

10M

XTAL2

Option 4

XTAL2

OSCICL

OSCICN

EN

Precision

Internal Oscillator

External

Oscillator

Drive Circuit

CLKSEL

Precision Internal Oscillator

External Oscillator

Low Power Internal Oscillator

smaRTClock Oscillator

CLKRDY

n

Clock Divider

SYSCLK

Low Power

Internal Oscillator

SmaRTClock

Oscillator

OSCXCN

Figure 19.1. Clocking Sources Block Diagram

The proper way of changing the system clock when both the clock source and the clock divide value are

being changed is as follows:

If switching from a fast “undivided” clock to a slower “undivided” clock:

a. Change the clock divide value.

b. Poll for CLKRDY > 1.

c. Change the clock source.

If switching from a slow “undivided” clock to a faster “undivided” clock:

a. Change the clock source.

b. Change the clock divide value.

c. Poll for CLKRDY > 1.

Rev. 1.3

191

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