C8051F91X-C8051F90X View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F91X-C8051F90X

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

IDLE

PCA0MD

CWW CCCE

I D D PPPC

DT L SSSF

LEC 210

K

PCA0CN

CCCCCCCC

FRCCCCCC

FFFFFF

543210

SYSCLK/12

000

SYSCLK/4

001

Timer 0 Overflow

010

ECI

011

SYSCLK

100

External Clock/8

101

SmaRTClock/8*

110

PCA0L

read

Snapshot

Register

To SFR Bus

0

PCA0H

PCA0L

Overflow

To PCA Interrupt System

1

CF

To PCA Modules

*Only available on ‘F912 and ‘F902 devices.

Figure 26.2. PCA Counter/Timer Block Diagram

26.2. PCA0 Interrupt Sources

Figure 26.3 shows a diagram of the PCA interrupt tree. There are eight independent event flags that can

be used to generate a PCA0 interrupt. They are: the main PCA counter overflow flag (CF), which is set

upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on an

overflow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA

channel (CCF0, CCF1, CCF2, CCF3, CCF4, and CCF5), which are set according to the operation mode of

that module. These event flags are always set when the trigger condition occurs. Each of these flags can

be individually selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF

for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any

individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by

setting the EA bit and the EPCA0 bit to logic 1.

294

Rev. 1.0

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