C8051F911-GM View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F911-GM

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

3. Pinout and Package Definitions

Name

VBAT

Table 3.1. Pin Definitions for the C8051F91x-C8051F90x

Pin Numbers

‘F912-GM ‘F912-GU

‘F902-GM ‘F902-GU

‘F911-GM ‘F911-GU

‘F901-GM ‘F901-GU

5

8

Type

P In

Description

Battery Supply Voltage.

C8051F911/01 devices:

Must be 0.9 to 1.8 V in single-cell battery mode and 1.8 to 3.6 V in

dual-cell battery mode.

C8051F912/02 devices:

Must be 0.9 to 3.6 V in single-cell battery mode and 1.8 to 3.6 V in

dual-cell battery mode.

VDD /

3

6

P In Power Supply Voltage. Must be 1.8 to 3.6 V. This supply voltage is

not required in low power sleep mode. This voltage must always

be > VBAT.

DC+

P Out

Positive output of the dc-dc converter. In single-cell battery mode,

a 1uF ceramic capacitor is required between DC+ and DC–. This

pin can supply power to external devices when operating in single-

cell battery mode.

DC– /

1

4

P In DC-DC converter return current path. In single-cell battery mode,

this pin is typically not connected to ground.

GND

GND

2

DCEN

4

G In dual-cell battery mode, this pin must be connected directly to

ground.

5

G Required Ground.

7

P In DC-DC Enable Pin. In single-cell battery mode, this pin must be

connected to VBAT through a 0.68 µH inductor.

G In dual-cell battery mode, this pin must be connected directly to

ground.

RST/

6

9

D I/O Device Reset. Open-drain output of internal POR or VDD monitor.

An external source can initiate a system reset by driving this pin

low for at least 15 µs. A 1 k to 5 k pullup to VDD is recom-

mended. See Section “18. Reset Sources” on page 171 Section

for a complete description.

C2CK

P2.7/

D I/O Clock signal for the C2 Debug Interface.

7

10

D I/O Port 2.7. This pin can only be used as GPIO. The Crossbar cannot

route signals to this pin and it cannot be configured as an analog

input. See Port I/O Section for a complete description.

C2D

D I/O

*Note: Available only on the C8051F912/02.

Bi-directional data signal for the C2 Debug Interface.

Rev. 1.0

27

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