C8051F91X-C8051F90X View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F91X-C8051F90X

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

14.1. Normal Mode

The MCU is fully functional in normal mode. Figure 14.1 shows the on-chip power distribution to various

peripherals. There are three supply voltages powering various sections of the chip: VBAT, VDD/DC+, and

the 1.8 V internal core supply. VREG0, PMU0 and the SmaRTClock are always powered directly from the

VBAT pin. All analog peripherals are directly powered from the VDD/DC+ pin, which is an output in one-cell

mode and an input in two-cell mode. All digital peripherals and the CIP-51 core are powered from the 1.8 V

internal core supply. The RAM is also powered from the core supply in Normal mode.

One-cell: 0.9 to 3.6 V (F912/02 devices only)

VBAT

One-cell: 0.9 to 1.8 V

Two-cell: 1.8 to 3.6 V

VDD/DC+

One-cell or Two-cell: 1.8 to 3.6 V

DC0

1.9 V

typical

One-Cell Active/

Idle/Stop/Suspend

One-Cell Sleep

Note: VDD/DC+ must be > VBAT

GPIO

Analog Peripherals

A

M

U

VREG0 X

VREF

10-bit

300 ksps

ADC

TEMP

SENSOR

IREF0

+

+

-

-

VOLTAGE

COMPARATORS

Sleep

Active/Idle/

Stop/Suspend 1.8 V Digital Peripherals

PMU0

SmaRTClock

RAM

CIP-51

Core

Flash

Timers

UART

SPI

SMBus

Figure 14.1. C8051F91x-C8051F90x Power Distribution

144

Rev. 1.0

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