C8051T603-GS(2007) View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051T603-GS
(Rev.:2007)

Mixed Signal OTP EPROM MCU Family

Silicon Laboratories 

C8051T600/1/2/3/4/5

The output of Comparator0 can be polled in software, used as an interrupt source, and/or routed to a Port

pin. When routed to a Port pin, the Comparator0 output is available asynchronous or synchronous to the

system clock; the asynchronous output is available even in STOP mode (with no system clock active).

When disabled, the Comparator0 output (if assigned to a Port I/O pin via the Crossbar) defaults to the logic

low state. See Section “13.1. Priority Crossbar Decoder” on page 98 for details on configuring the

Comparator0 output via the digital Crossbar. Comparator0 inputs can be externally driven from –0.25 V to

(VDD + 0.25 V) without damage or upset. The complete electrical specifications for Comparator0 are given

in Table 7.1.

The Comparator0 response time may be configured in software via the CP0MD1–0 bits in register

CPT0MD (see SFR Definition 7.3). Selecting a longer response time reduces the amount of power con-

sumed by Comparator0. See Table 7.1 for complete timing and power consumption specifications.

CP0+

VIN+

VIN- CP0-

+

CP0

_

OUT

CIRCUIT CONFIGURATION

Positive Hysteresis Voltage

(Programmed with CP0HYP Bits)

VIN-

INPUTS

VIN+

Negative Hysteresis Voltage

(Programmed by CP0HYN Bits)

VOH

OUTPUT

VOL

Positive Hysteresis

Disabled

Negative Hysteresis

Disabled

Maximum

Positive Hysteresis

Maximum

Negative Hysteresis

Figure 7.2. Comparator Hysteresis Plot

The hysteresis of Comparator0 is software-programmable via its Comparator0 Control register (CPT0CN).

The user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive

and negative-going symmetry of this hysteresis around the threshold voltage.

The Comparator0 hysteresis is programmed using Bits3–0 in the Comparator0 Control Register CPT0CN

(shown in SFR Definition 7.1). The amount of negative hysteresis voltage is determined by the settings of

the CP0HYN bits. The amount of positive hysteresis can be programmed using the CP0HYP bits.

Comparator0 interrupts can be generated on both rising-edge and falling-edge output transitions. (For

Interrupt enable and priority control, see Section “9.3. Interrupt Handler” on page 70). The CP0FIF flag

is set to logic 1 upon a Comparator0 falling-edge interrupt, and the CP0RIF flag is set to logic 1 upon the

48

Rev. 0.5

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