C8051T600-GS(2007) View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051T600-GS
(Rev.:2007)

Mixed Signal OTP EPROM MCU Family

Silicon Laboratories 

C8051T600/1/2/3/4/5

1.1.3. Additional Features

The C8051T600/1/2/3/4/5 SoC family includes several key enhancements to the CIP-51 core and peripher-

als to improve performance and ease of use in end applications.

The extended interrupt handler provides 12 interrupt sources into the CIP-51, allowing numerous analog

and digital peripherals to interrupt the controller. An interrupt driven system requires less intervention by

the MCU, giving it more effective throughput. The extra interrupt sources are very useful when building

multi-tasking, real-time systems.

Several reset sources are available: power-on reset circuitry (POR), a Supply Monitor, a Watchdog Timer,

a Missing Clock Detector, a voltage level detection from Comparator0, a forced software reset, an external

reset pin, and an illegal OTP read/write detection. Each reset source except for the POR, Reset Input Pin,

and OTP protection may be disabled by the user in software. The WDT may be permanently enabled in

software after a power-on reset during MCU initialization.

The internal oscillator is factory calibrated to 24.5 MHz, and is accurate to ±2% over the entire operating

supply and temperature range. The internal oscillator can be directly divided by factors of 2, 4, or 8 to pro-

vide slower internal clock options. An external oscillator input is also included, allowing an external CMOS

clock, external capacitor, or external RC circuit to generate the system clock. If desired, the system clock

source may be switched on-the-fly to the external oscillator circuit. An external oscillator can be extremely

useful in low power applications, allowing the MCU to run from a slower (power saving) external clock

source, while periodically switching to the internal oscillator when faster operation is required.

P0.x

P0.y

EXTCLK

Internal

Oscillator

External

Clock

Source

Comparator 0

+

-

C0RSEF

Missing

Clock

Detector

(one-

shot)

EN

Supply

Monitor

Power On

Reset

'0'

(wired-OR)

PCA

WDT

EN

(Software Reset)

SWRSF

Reset

Funnel

Illegal OTP

operation

System

Clock

Clock Select

CIP-51

Microcontroller System Reset

Core

Extended Interrupt

Handler

Figure 1.3. On-Chip Clock and Reset

/RST

Rev. 0.5

17

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