C8051F38C-GMR View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F38C-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

Each time a capture event is received, the contents of the Timer 2 registers (TMR2H:TMR2L) are latched

into the Timer 2 Reload registers (TMR2RLH:TMR2RLL). A Timer 2 interrupt is generated if enabled.

TMR2CN

TTTTTTTT

FFF 2 2R2 2

2 2 2CS2CX

HL LEP SC

E L SL

NI

K

T

CKCON

TTTTTTSS

3 3 2 2 1 0CC

MMMMMMA A

HLHL 10

SYSCLK / 12

0

External Clock / 8

1

SYSCLK

0

TR2

1

TL2

Overflow

To SMBus

TCLK TMR2L TMR2H

To ADC,

SMBus

USB Start-of-Frame (SOF)

Low-Frequency Oscillator

Falling Edge

0

Capture TMR2RLL TMR2RLH

1

T2CSS

Enable

Interrupt

Figure 26.6. Timer 2 Capture Mode (T2SPLIT = 0)

When T2SPLIT = 1, the Timer 2 registers (TMR2H and TMR2L) act as two 8-bit counters. Each counter

counts up independently and overflows from 0xFF to 0x00. Each time a capture event is received, the con-

tents of the Timer 2 registers are latched into the Timer 2 Reload registers (TMR2RLH and TMR2RLL). A

Timer 2 interrupt is generated if enabled.

276

Rev. 1.4

Share Link: