C8051F362-GM2 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F362-GM2

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 20.3. SPI0CKR: SPI0 Clock Rate

SFR Page: all pages

SFR Address: 0xA2

R/W

R/W

SCR7 SCR6

Bit7

Bit6

R/W

SCR5

Bit5

R/W

SCR4

Bit4

R/W

SCR3

Bit3

R/W

SCR2

Bit2

R/W

SCR1

Bit1

R/W

SCR0

Bit0

Reset Value

00000000

Bits 7–0: SCR7–SCR0: SPI0 Clock Rate.

These bits determine the frequency of the SCK output when the SPI0 module is configured

for master mode operation. The SCK clock frequency is a divided version of the system

clock, and is given in the following equation, where SYSCLK is the system clock frequency

and SPI0CKR is the 8-bit value held in the SPI0CKR register.

fSCK = 2-----×-----(--S--S--P-Y---I-S-0--C-C----L-K--K--R-----+-----1----)

for 0 <= SPI0CKR <= 255

Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,

fSCK = 2---2--×-0---0-(--40---0--+-0---0-1---)

fSCK = 200kHz

SFR Definition 20.4. SPI0DAT: SPI0 Data

SFR Page: all pages

SFR Address: 0xA3

R/W

R/W

Bit7

Bit6

R/W

Bit5

R/W

Bit4

R/W

Bit3

R/W

Bit2

R/W

Bit1

R/W

Reset Value

00000000

Bit0

Bits 7–0: SPI0DAT: SPI0 Transmit and Receive Data.

The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to SPI0DAT

places the data into the transmit buffer and initiates a transfer when in Master Mode. A read

of SPI0DAT returns the contents of the receive buffer.

Rev. 1.0

243

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