C8051F364 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F364

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

Table 19.7. Timer Settings for Standard Baud Rates Using the PLL

Frequency: 50.0 MHz

Target

Baud Rate

(bps)

230400

115200

57600

28800

14400

9600

2400

Baud Rate

% Error

0.45%

–0.01%

0.45%

–0.01%

0.22%

–0.01%

–0.01%

Oscilla-

tor Divide

Factor

218

434

872

1736

3480

5208

20832

Timer Clock

Source

SYSCLK

SYSCLK

SYSCLK/4

SYSCLK/4

SYSCLK/12

SYSCLK/12

SYSCLK/48

SCA1-SCA0

(pre-scale select)1

XX2

XX

01

01

00

00

10

T1M1

1

1

0

0

0

0

0

Timer 1

Reload

Value (hex)

0x93

0x27

0x93

0x27

0x6F

0x27

0x27

Notes:

1. SCA1–SCA0 and T1M bit definitions can be found in Section 21.1.

2. X = Don’t care.

Table 19.8. Timer Settings for Standard Baud Rates Using the PLL

Frequency: 100.0 MHz

Target

Baud Rate

(bps)

230400

115200

Baud Rate

% Error

–0.01%

0.45%

Oscilla-

tor Divide

Factor

434

872

Timer Clock SCA1-SCA0

Source (pre-scale select)1

SYSCLK

XX2

SYSCLK/4

01

57600

–0.01%

1736

SYSCLK/4

01

28800

0.22%

3480 SYSCLK/12

00

14400

–0.47%

6912 SYSCLK/48

10

9600

0.45%

10464 SYSCLK/48

10

Notes:

1. SCA1–SCA0 and T1M bit definitions can be found in Section 21.1.

2. X = Don’t care.

T1M1

1

0

0

0

0

0

Timer 1

Reload

Value (hex)

0x27

0x93

0x27

0x6F

0xB8

0x93

Rev. 1.0

233

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