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C8051F007 View Datasheet(PDF) - Silicon Laboratories

Part Name
Description
MFG CO.
C8051F007
Silabs
Silicon Laboratories 
C8051F007 Datasheet PDF : 171 Pages
First Prev 61 62 63 64 65 66 67 68 69 70 Next Last
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
10.3. SPECIAL FUNCTION REGISTERS
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers (SFRs). The
SFRs provide control and data exchange with the CIP-51’s resources and peripherals. The CIP-51 duplicates the
SFRs found in a typical 8051 implementation as well as implementing additional SFRs used to configure and access
the sub-systems unique to the MCU. This allows the addition of new functionality while retaining compatibility
with the MCS-51™ instruction set. Table 10.3 lists the SFRs implemented in the CIP-51 System Controller.
The SFR registers are accessed any time the direct addressing mode is used to access memory locations from 0x80
to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g. P0, TCON, P1, SCON, IE, etc.) are bit-addressable as well
as byte-addressable. All other SFRs are byte-addressable only. Unoccupied addresses in the SFR space are
reserved for future use. Accessing these areas will have an indeterminate effect and should be avoided. Refer to the
corresponding pages of the datasheet, as indicated in Table 10.3, for a detailed description of each register.
F8 SPI0CN
F0 B
E8 ADC0CN
E0 ACC
D8 PCA0CN
D0 PSW
C8 T2CON
C0 SMB0CN
B8 IP
B0 P3
A8 IE
A0 P2
98 SCON
90 P1
88 TCON
80 P0
0(8)
Table 10.2. Special Function Register Memory Map
PCA0H
PCA0L
XBR0
PCA0MD
REF0CN
SMB0STA
OSCXCN
SBUF
TMR3CN
TMOD
SP
1(9)
PCA0CPH0
PCA0CPL0
XBR1
PCA0CPM0
DAC0L
RCAP2L
SMB0DAT
AMX0CF
OSCICN
SPI0CFG
TMR3RLL
TL0
DPL
2(A)
PCA0CPH1
PCA0CPL1
XBR2
PCA0CPM1
DAC0H
RCAP2H
SMB0ADR
AMX0SL
SPI0DAT
TMR3RLH
TL1
DPH
3(B)
PCA0CPH2
PCA0CPL2
PCA0CPM2
DAC0CN
TL2
ADC0GTL
ADC0CF
PRT0CF
TMR3L
TH0
4(C)
PCA0CPH3
PCA0CPL3
PCA0CPM3
DAC1L
TH2
ADC0GTH
PRT1IF
PRT1CF
SPI0CKR
TMR3H
TH1
5(D)
PCA0CPH4
EIP1
PCA0CPL4
EIE1
PCA0CPM4
DAC1H
ADC0LTL
ADC0L
FLSCL
PRT2CF
CPT0CN
CKCON
6(E)
WDTCN
EIP2
RSTSRC
EIE2
DAC1CN
SMB0CR
ADC0LTH
ADC0H
FLACL***
EMI0CN***
PRT3CF
CPT1CN
PSCTL
PCON
7(F)
Bit Addressable
Table 10.3. Special Function Registers
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
* Refers to a register in the C8051F000/1/2/5/6/7 only.
** Refers to a register in the C8051F010/1/2/5/6/7 only.
*** Refers to a register in the C8051F005/06/07/15/16/17 only.
Address Register
0xE0
0xBC
0xE8
0xC5
0xC4
0xBF
0xBE
ACC
ADC0CF
ADC0CN
ADC0GTH
ADC0GTL
ADC0H
ADC0L
Description
Accumulator
ADC Configuration
ADC Control
ADC Greater-Than Data Word (High Byte)
ADC Greater-Than Data Word (Low Byte)
ADC Data Word (High Byte)
ADC Data Word (Low Byte)
Page No.
76
33*, 42**
34*, 45**
36*, 47**
36*, 47**
35*, 46**
35*, 46**
Rev. 1.7
70

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