C8051F007 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
C8051F007 Datasheet PDF : 171 Pages
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.4. Programmable Digital I/O and Crossbar
The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. All four ports are pinned out on the
F000/05/10/15. Ports 0 and 1 are pinned out on the F001/06/11/16, and only Port 0 is pinned out on the
F002/07/12/17. The Ports not pinned out are still available for software use as general purpose registers. The Port
I/O behave like the standard 8051 with a few enhancements.
Each Port I/O pin can be configured as either a push-pull or open-drain output. Also, the “weak pull-ups” which are
normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for low power
applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is essentially a large digital switching network
that allows mapping of internal digital system resources to Port I/O pins on P0, P1, and P2. (See Figure 1.8.)
Unlike microcontrollers with standard multiplexed digital I/O, all combinations of functions are supported.
The on-board counter/timers, serial buses, HW interrupts, ADC Start of Conversion input, comparator outputs, and
other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar
Control registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources
needed for his particular application.
Figure 1.8. Digital Crossbar Diagram
Highest
Priority
Lowest
Priority
Port
Latches
2
SMBus
4
SPI
2
UART
6
PCA
Comptr.
2
Outputs
T0, T1,
6
T2
SYSCLK
CNVSTR
8
P0 (P0.0-P0.7)
8
P1 (P1.0-P1.7)
8
P2 (P2.0-P2.7)
8
P3 (P3.0-P3.7)
XBR0, XBR1,
XBR2 Registers
PRT0CF, PRT1CF,
PRT2CF Registers
Priority
Decoder
8
Digital
Crossbar
8
P0
I/O
Cells
P1
I/O
Cells
8
P2
I/O
Cells
PRT3CF
Register
P3
I/O
Cells
External
Pins
P0.0
P0.7
Highest
Priority
P1.0
P1.7
P2.0
P2.7
Lowest
Priority
P3.0
P3.7
Rev. 1.7
16
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