LTC1289CCSW(RevB) View Datasheet(PDF) - Linear Technology

Part Name

Description

MFG CO.

LTC1289CCSW
(Rev.:RevB)

3 Volt Single Chip 12-Bit Data Acquisition System

Linear Technology 

LTC1289

TYPICAL APPLICATI S

SNEAK-A-BIT Code

DOUT from LTC1289 in MC68HC05C4 RAM

Sign

Location $77 B12 B11 B10 B9 B8 B7 B6 B5

LSB

Location $87 B4 B3 B2 B1 B0 filled with 0s

DIN words for LTC1289

MUX Addr.

MSBF

(ODD/SIGN)

UNI

Word

Length

DIN1 0 0 1 1 1 1 1 1

DIN2 0 1 1 1 1 1 1 1

DIN3

00111111

LTC1289 TA05

SNEAK-A-BIT Code for the LTC1289 Using the MC68HC05C4

MNEMONIC

DESCRIPTION

READ – / + :

LDA #$50

STA $0A

LDA #$FF

STA $06

BSET 0, $02

JSR READ –/+

JSR READ +/–

JSR READ –/+

JSR CHK SIGN

LDA #$3F

JSR TRANSFER

LDA $60

STA $71

LDA $61

STA $72

RTS

Configuration data for SPCR

Load configuration data into $0A

Configuration data for port C DDR

Load configuration data into port C DDR

Make sure CS is high

Dummy read configures LTC1289 for

next read

Read CH6 with respect to CH7

Read CH7 with respect to CH6

Determines which reading has valid

data, converts to 2's complement and

stores in RAM

Load DIN word for LTC1289 into ACC

Read LTC1289 routine

Load MSBs from LTC1289 in ACC

Store MSBs in $71

Load LSBs from LTC1289 in ACC

Store LSBs in $72

Return

SNEAK-A-BIT Code for the LTC1289 Using the MC68HC05C4

MNEMONIC

DESCRIPTION

READ +/–: LDA #$7F

JSR TRANSFER

LDA $60

STA $73

LDA $61

STA $74

RTS

TRANSFER: BCLR 0, $02

STA $0C

LOOP 1: TST $0B

BPL LOOP 1

LDA $0C

STA $0C

STA $60

LOOP 2: TST $0B

BPL LOOP 2

BSET 0, $02

LDA $0C

STA $61

RTS

CHK SIGN: LDA $73

ORA $74

BEQ MINUS

CLC

ROR $73

ROR $74

LDA $73

STA $77

LDA $74

STA $87

BRA END

MINUS: CLC

ROR $71

ROR $72

COM $71

COM $72

LDA $72

ADD #$01

STA $72

CLRA

ADC $71

STA $71

STA $77

LDA $72

STA $87

END:

RTS

Load DIN word for LTC1289 into ACC

Read LTC1289 routine

Load MSBs from LTC1289 into ACC

Store MSBs in $73

Load LSBs from LTC1289 into ACC

Store LSBs in $74

Return

CS goes low

Load DIN into SPI. Start transfer

Test status of SPIF

Loop to previous instruction if not done

Load contents of SPI data reg into ACC

Start next cycle

Store MSBs in $60

Test status of SPIF

Loop to previous instruction if not done

CS goes high

Load contents of SPI data reg into ACC

Store LSBs in $61

Return

Load MSBs of +/– read into ACC

Or ACC (MSBs) with LSBs of +/– read

If result is 0 goto minus

Clear carry

Rotate right $73 through carry

Rotate right $74 through carry

Load MSBs of +/– read into ACC

Store MSBs in RAM locations $77

Load LSBs of +/– read into ACC

Store LSBs in RAM location $87

Goto end of routine

Clear carry

Shift MSBs of –/+ read right

Shift LSBs of –/+ read right

1's complement of MSBs

1's complement of LSBs

Load LSBs into ACC

Add 1 to LSBs

Store ACC in $72

Clear ACC

Add with carry to MSBs. Result in ACC

Store ACC in $71

Store MSBs in RAM locations $77

Load LSBs in ACC

Store LSBs in RAM location $87

Return

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