AM79C970AVC View Datasheet(PDF) - Advanced Micro Devices
Part Name
Description
MFG CO.
AM79C970AVC
Advanced Micro Devices
AM79C970AVC Datasheet PDF : 220 Pages
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which the PCnet-PCI II controller
will store incoming frame data.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET or by
setting the STOP bit.
CSR24: Base Address of Receive Descriptor
Ring Lower
Bit Name
Description
31–16 RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0 BADRL
Contains the lower 16 bits of the
base address of the receive de-
scriptor ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET or by
setting the STOP bit.
CSR25: Base Address of Receive Descriptor
Ring Upper
Bit Name
Description
31–16 RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0 BADRU
Contains the upper 16 bits of the
base address of the receive de-
scriptor ring.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET or by
setting the STOP bit.
CSR26: Next Receive Descriptor Address Lower
Bit Name
Description
31–16 RES
15–0 NRDAL
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
next receive descriptor address
pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET or by
setting the STOP bit.
CSR27: Next Receive Descriptor Address Upper
Bit Name
Description
31–16 RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0 NRDAU
Contains the upper 16 bits of the
next receive descriptor address
pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET or by
setting the STOP bit.
CSR28: Current Receive Descriptor Address Lower
Bit Name
Description
31–16 RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0 CRDAL
Contains the lower 16 bits of the
current receive descriptor ad-
dress pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET or by
setting the STOP bit.
CSR29: Current Receive Descriptor Address Upper
Bit Name
Description
31–16 RES
Reserved locations. Written as
ZEROs and read as undefined.
15–0 CRDAU
Contains the upper 16 bits of the
current receive descriptor ad-
dress pointer.
Read/Write accessible only when
either the STOP or the SPND bit
is set. These bits are unaffected
by H_RESET, S_RESET or by
setting the STOP bit.
CSR30: Base Address of Transmit Descriptor
Ring Lower
Bit Name
Description
31–16 RES
15–0 BADXL
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
base address of the transmit de-
scriptor ring.
Read/Write accessible only when
either the STOP or the SPND bit
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Am79C970A
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