ADSP-21364YSWZ-2AA(RevJ) View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

ADSP-21364YSWZ-2AA
(Rev.:RevJ)

SHARC Processors

Analog Devices 

ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366

S/PDIF Receiver

The following section describes timing as it relates to the

S/PDIF receiver. This feature is not available on the

ADSP-21363 processors.

Internal Digital PLL Mode

In the internal digital phase-locked loop mode the internal PLL

(digital PLL) generates the 512 × FS clock.

Table 38. S/PDIF Receiver Output Timing (Internal Digital PLL Mode)

Parameter

Switching Characteristics

tDFSI

Frame Sync Delay After Serial Clock

tHOFSI

Frame Sync Hold After Serial Clock

tDDTI

Transmit Data Delay After Serial Clock

tHDTI

tSCLKIW1

Transmit Data Hold After Serial Clock

Transmit Serial Clock Width

1 Serial clock frequency is 64 ×FS where FS = the frequency of frame sync.

Min

Max

Unit

5

ns

–2

ns

5

ns

–2

ns

38

ns

DRIVE EDGE

DAI_P20–1

(SCLK)

DAI_P20–1

(FS)

DAI_P20–1

(DATA CHANNEL

A/B)

tDFSI

tHOFSI

tDDTI

tHDTI

tSCLKIW

SAMPLE EDGE

Figure 33. S/PDIF Receiver Internal Digital PLL Mode Timing

Rev. J | Page 41 of 60 | July 2013

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