ADS6443IRGCR View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ADS6443IRGCR Datasheet PDF : 75 Pages
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Table 22. Minimum Clock Amplitude across gains
ADS6445, ADS6444
ADS6443, ADS6442
SLAS531 – MAY 2007
CLOCK BUFFER GAIN
Gain 0 (minimum gain)
Gain 1 (default gain)
Gain 2
Gain 3
Gain 4 (highest gain)
MINIMUM CLOCK AMPLITUDE SUPPORTED
mVPP differential
800
400
300
200
150
POWER DOWN MODES
The ADS644X has three power down modes – global power down, channel standby and input clock stop.
Global Power Down
This is a global power down mode in which almost the entire chip is powered down, including the four ADCs,
internal references, PLL and LVDS buffers. As a result, the total power dissipation falls to about 77 mW typical
(with input clock running). This mode can be initiated by setting the register bit <PDN GLOBAL> (refer to
Table 13). The output data and clock buffers are in high impedance state.
The wake-up time from this mode to data becoming valid in normal mode is 100 µs.
Channel Standby
In this mode, only the ADC of each channel is powered down and this helps to get very fast wake-up times.
Each of the four ADCs can be powered down independently using the register bits <PDN CH> (refer to
Table 13). The output LVDS buffers remain powered up.
The wake-up time from this mode to data becoming valid in normal mode is 200 clock cycles.
Input Clock Stop
The converter enters this mode:
• If the input clock frequency falls below 1 MSPS or
• If the input clock amplitude is less than 400 mVPP, differential with default clock buffer gain setting) at any
sampling frequency.
All ADCs and LVDS buffers are powered down and the power dissipation is about 235 mW. The wake-up time
from this mode to data becoming valid in normal mode is 100 µs.
Table 23. Power Down Modes Summary
POWER DOWN MODE
In power-up
Global power down
1 Channel in standby
2 Channels in standby
3 Channels in standby
4 Channels in standby
Input clock stop
AVDD POWER
(mW)
1360
65
1115 (1)
825 (1)
532 (1)
245 (1)
200
LVDD POWER
(mW)
297
12
297 (1)
297 (1)
297 (1)
297 (1)
35
(1) Sampling frequency = 125 MSPS.
WAKE UP TIME
–
100 µs
200 Clocks
200 Clocks
200 Clocks
200 Clocks
100 µs
POWER SUPPLY SEQUENCING
During power-up, the AVDD and LVDD supplies can come up in any sequence. The two supplies are separated
inside the device. Externally, they can be driven from separate supplies or from a single supply.
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