CS4341A-KS(2002) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS4341A-KS
(Rev.:2002)

24-Bit, 192 kHz Stereo DAC with Volume Control

Cirrus Logic 

CS4341A

SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Continued)

Parameter

SPI Mode

CCLK Clock Frequency

RST Rising Edge to CS Falling

CCLK Edge to CS Falling

CS High Time Between Transmissions

CS Falling to CCLK Edge

CCLK Low Time

CCLK High Time

CDIN to CCLK Rising Setup Time

CCLK Rising to DATA Hold Time

Rise Time of CCLK and CDIN

Fall Time of CCLK and CDIN

Symbol

(Note 6)

(Note 7)

(Note 8)

(Note 8)

fsclk

tsrs

tspi

tcsh

tcss

tscl

tsch

tdsu

tdh

tr2

tf2

Min

-

500

500

1.0

20

66

66

40

15

-

-

Max

Unit

6

MHz

-

ns

-

ns

-

µs

-

ns

-

ns

-

ns

-

ns

-

ns

100

ns

100

ns

Notes: 6. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

7. Data must be held for sufficient time to bridge the transition time of CCLK.

8. For fsclk < 1 MHz.

RST

t srs

CS

CCLK

C D IN

t spi t css

t scl t sch

t csh

t r2

t f2

t dsu t dh

Figure 21. Control Port Timing - SPI Mode

28

DS582PP1

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