CS4341A(2002) View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS4341A Datasheet PDF : 32 Pages
| |||
CS4341A
SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Inputs: Logic
0 = AGND, Logic 1 = VA)
Parameter
Symbol
Min
I2C Mode
SCL Clock Frequency
fscl
-
RST Rising Edge to Start
tirs
500
Bus Free Time Between Transmissions
tbuf
4.7
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
Clock Low time
tlow
4.7
Clock High Time
thigh
4.0
Setup Time for Repeated Start Condition
tsust
4.7
SDA Hold Time from SCL Falling
(Note 5)
thdd
0
SDA Setup time to SCL Rising
tsud
250
Rise Time of SCL and SDA
trc, trc
-
Fall Time SCL and SDA
tfc, tfc
-
Setup Time for Stop Condition
tsusp
4.7
Max
100
-
-
-
-
-
-
-
-
1
300
-
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
Notes: 5. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
RST
t irs
S to p
S ta rt
SDA
t buf
t hdst
t high
R e pe ate d
S ta rt t rd
t hdst
S to p
t fd
t fc
t susp
SCL
t
lo w
t
hdd
t sud t ack
t sust
t rc
Figure 20. Control Port Timing - I2C Mode
DS582PP1
27
Share Link: 